公开(公告)号：US10927000B2

公开(公告)日：2021-02-23

申请号：US15295997

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81B3/00 ,  B81C1/00

Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

公开(公告)号：US09954108B2

公开(公告)日：2018-04-24

申请号：US15458035

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

公开(公告)号：US20170186872A1

公开(公告)日：2017-06-29

申请号：US15458035

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

公开(公告)号：US20170125595A1

公开(公告)日：2017-05-04

申请号：US14954967

申请日：2015-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/32105 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795

Abstract: A semiconductor structure includes a semiconductor substrate, at least a semiconductor layer formed on the semiconductor substrate, and at least a fin structure formed on the semiconductor layer. The semiconductor substrate includes a first semiconductor material, the semiconductor layer includes the first semiconductor material and a second semiconductor material, and the fin structure includes at least the first semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The semiconductor layer includes a first width, the fin structure includes a second width, and the second width is smaller than the first width.

公开(公告)号：US12274087B2

公开(公告)日：2025-04-08

申请号：US17990763

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Chung-Yi Chiu

IPC: H10D62/80 ,  H10D30/01 ,  H10D30/60 ,  H10D62/13 ,  H10D62/17 ,  H10D62/83 ,  H10D64/27

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

公开(公告)号：US20250098272A1

公开(公告)日：2025-03-20

申请号：US18969191

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20250054883A1

公开(公告)日：2025-02-13

申请号：US18244320

申请日：2023-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L23/64 ,  H01L23/498

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

公开(公告)号：US20240213304A1

公开(公告)日：2024-06-27

申请号：US18107521

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L27/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0647

Abstract: An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

公开(公告)号：US20230402288A1

公开(公告)日：2023-12-14

申请号：US17857158

申请日：2022-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31111 ,  H01L21/76802 ,  H01L21/31144

Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

公开(公告)号：US20230369436A1

公开(公告)日：2023-11-16

申请号：US17837054

申请日：2022-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.