公开(公告)号：US20190096892A1

公开(公告)日：2019-03-28

申请号：US16162340

申请日：2018-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC: H01L27/11 ,  G11C11/412 ,  G11C7/18 ,  G11C8/14 ,  G11C5/06

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

公开(公告)号：US10153287B1

公开(公告)日：2018-12-11

申请号：US15795247

申请日：2017-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/78 ,  H01L23/528 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.

公开(公告)号：US20180182766A1

公开(公告)日：2018-06-28

申请号：US15422471

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Ping Huang ,  Chun-Hsien Huang ,  Yu-Tse Kuo ,  Ching-Cheng Lung

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C7/02 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4125 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1116

Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

公开(公告)号：US09947674B2

公开(公告)日：2018-04-17

申请号：US15686169

申请日：2017-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09947673B1

公开(公告)日：2018-04-17

申请号：US15479253

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Chia Chang ,  Shih-Hao Liang ,  Chun-Yen Tseng ,  Yu-Tse Kuo ,  Ching-Cheng Lung ,  Hung-Chan Lin ,  Shao-Hui Wu

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/412 ,  H01L29/24

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/24

Abstract: The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.

公开(公告)号：US09871048B1

公开(公告)日：2018-01-16

申请号：US15621754

申请日：2017-06-13

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.

公开(公告)号：US20170294429A1

公开(公告)日：2017-10-12

申请号：US15092630

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yung-Feng Cheng ,  Yu-Tse Kuo ,  Chia-Wei Huang ,  Li-Ping Huang ,  Shu-Ru Wang

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

公开(公告)号：US20140035111A1

公开(公告)日：2014-02-06

申请号：US14062914

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Meng-Ping Chuang ,  Yu-Tse Kuo ,  Chia-Chun Sun ,  Yun-San Huang

IPC: H01L29/06

CPC classification number: H01L29/0692 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0684

Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Abstract translation: 存储单元阵列的布局配置至少包括具有第一导电类型的梳状掺杂区域和具有第二导电类型的鱼骨形掺杂区域。 第二导电类型和第一导电类型是互补的。 此外，梳状掺杂区域和鱼骨形掺杂区域是交错的。

公开(公告)号：US20250040228A1

公开(公告)日：2025-01-30

申请号：US18916723

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20240349515A1

公开(公告)日：2024-10-17

申请号：US18755693

申请日：2024-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/80

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.