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公开(公告)号：US20090117737A1
公开(公告)日：2009-05-07
申请号：US12178072
申请日：2008-07-23
CPC分类号： G03F7/70441 , G03F1/36 , H01L21/0335 , H01L21/32139 , H01L21/76838
摘要： Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.
摘要翻译： 公开了形成相邻多导体线端的方法及其掩模。 在一个实施例中，该方法包括在隔离区域上形成多导体层; 在所述多导体层上形成掩模，所述掩模包括形成多导体线端的形状和校正元件，以确保多导体线的设计接近端; 以及使用图案化的光致抗蚀剂掩模蚀刻多导体层以产生相邻的多导体线端，其中在蚀刻期间去除校正元件。
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公开(公告)号：US20090065956A1
公开(公告)日：2009-03-12
申请号：US11853358
申请日：2007-09-11
IPC分类号： H01L23/48
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over an isolation region adjacent to the first active region; and a second device having a second conductive line extending over one of a second active region and a contact element and having a second line end of the second conductive line positioned over the isolation region adjacent to the one of the second active region and the contact element, wherein the first line end and the second line end each include a bulbous end that is distanced from a respective active region or contact element.
摘要翻译： 公开了形成线端的方法和包括线端的相关存储单元。 在一个实施例中，存储单元包括fa第一器件，其具有在第一有源区上延伸的第一导线，并且第一导线的第一线端位于与第一有源区相邻的隔离区上; 以及第二装置，具有延伸到第二有源区和接触元件之一上的第二导线，并且第二导线的第二线端位于与第二有源区和接触元件中的一个相邻的隔离区上方 ，其中所述第一线端和所述第二线端各自包括与相应的有源区域或接触元件间隔开的球状端。
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公开(公告)号：US20080286683A1
公开(公告)日：2008-11-20
申请号：US11750026
申请日：2007-05-17
申请人： Colin J. Brodsky , Allen H. Gabor , Javier Perez
发明人： Colin J. Brodsky , Allen H. Gabor , Javier Perez
CPC分类号： G03F7/0035
摘要： A method and a structure. The structure includes: a solid core comprising a first photoresist material, the core having a bottom surface on a substrate, a top surface and opposite first and second side surfaces between the top surface and the bottom surface; and a shell comprising a second photoresist material, the shell on the top surface of the substrate, the shell containing a cavity open to the top surface of the substrate, the shell formed over the top surface and the first and second side surfaces walls of the core, the core completely filling the cavity. The core is stiffer than the shell. The method includes: forming the core from a first photoresist layer and forming the shell from a second photoresist layer applied over the core. The core may be cross-linked to increase its stiffness.
摘要翻译： 一种方法和结构。 该结构包括：固体芯，其包括第一光致抗蚀剂材料，所述芯在基底上具有底表面，顶表面以及在顶表面和底表面之间的相对的第一和第二侧表面; 以及壳体，其包括第二光致抗蚀剂材料，所述壳体在所述基板的顶表面上，所述外壳包含通向所述基板的顶表面的空腔，所述外壳形成在所述顶表面上以及所述第一和第二侧表面壁上 核心，核心完全填充空腔。 核心比壳更僵硬。 该方法包括：从第一光致抗蚀剂层形成芯并从施加在芯上的第二光致抗蚀剂层形成壳。 芯可以交联以增加其刚度。
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公开(公告)号：US07393703B2
公开(公告)日：2008-07-01
申请号：US11382489
申请日：2006-05-10
申请人： Brent Alan Anderson , Shahid Ahmad Butt , Allen H. Gabor , Patrick Edward Lindo , Edward Joseph Nowak , Jed Hickory Rankin
发明人： Brent Alan Anderson , Shahid Ahmad Butt , Allen H. Gabor , Patrick Edward Lindo , Edward Joseph Nowak , Jed Hickory Rankin
CPC分类号： H01L22/20
摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.
摘要翻译： 一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。 该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数 在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。
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公开(公告)号：US07354779B2
公开(公告)日：2008-04-08
申请号：US11276707
申请日：2006-03-10
CPC分类号： H01L21/0271 , H01L21/0276
摘要： Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the variable depth is modulated based on the local topography of the wafer. The resultant topography of the applied film and wafer is substantially planar (e.g., within approximately 100 nm) across the wafer.
摘要翻译： 公开了在半导体晶片制造工艺中应用地形学补偿膜的方法。 这些过程包括预先处理晶片的表面，以便确定晶片的局部形貌（例如，z-高度），然后将薄膜的可变深度施加到晶片，使得可变深度基于本地 晶圆的形貌。 所施加的膜和晶片的所得形貌在晶片上基本上是平面的（例如在大约100nm内）。
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36.发明授权Method for performing chemical shrink process over BARC (bottom anti-reflective coating) 失效在BARC（底部防反射涂层）上进行化学收缩工艺的方法公开(公告)号：US07288478B2
公开(公告)日：2007-10-30
申请号：US11160670
申请日：2005-07-05
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0273 , H01L21/31144 , H01L21/76816 , Y10T428/24322 , Y10T428/24331 , Y10T428/24521 , Y10T428/249953
摘要： A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist hole; etching the BARC layer through the photoresist hole to extend the photoresist hole to the hole layer; performing the chemical shrinking process to shrink the extended photoresist hole; and etching the hole layer through the shrunk, extended photoresist hole so as to form a hole in the hole layer.
摘要翻译： 一种结构及其形成方法。 该方法包括提供一种结构，其包括（a）空穴层，（b）在空穴层顶部的BARC（底部抗反射涂层）层，和（c）在BARC层的顶部上的图案化光致抗蚀剂层， 光致抗蚀剂孔; 通过光致抗蚀剂孔蚀刻BARC层以将光致抗蚀剂孔延伸到孔层; 执行化学收缩过程以收缩延伸的光致抗蚀剂孔; 并且通过收缩的延伸的光致抗蚀剂孔蚀刻孔层，以在孔层中形成孔。
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公开(公告)号：US06964032B2
公开(公告)日：2005-11-08
申请号：US10378579
申请日：2003-02-28
IPC分类号： G03F1/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70125 , G06F17/5068 , G06F2217/12
摘要： A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.
摘要翻译： 提供了一种设计用于对集成电路（IC）设计布局进行成像的掩模的方法，以有效地配置对应于光刻投影系统的最佳配置的环形照明源的分解辅助特征（SRAF）。 确定IC设计的关键音调，并且确定环形照明光源的最佳内外径向坐标，以便通过掩模投射的所得图像将针对设计布局中的全部音高进行优化。 提供了用于确定环形照明源的最佳内半径和外半径的关系。 将SRAF的数量和位置添加到掩模设计中，使得所得到的间距范围基本上对应于临界间距。 配置SRAF的方法是使图像具有最佳特征，如良好的对比度和良好的聚焦深度。
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公开(公告)号：US5318877A
公开(公告)日：1994-06-07
申请号：US155796
申请日：1993-11-22
申请人： Christopher K. Ober , Allen H. Gabor , Eric A. Lehner , Guoping Mao , Lizabeth A. Schneggenburger
发明人： Christopher K. Ober , Allen H. Gabor , Eric A. Lehner , Guoping Mao , Lizabeth A. Schneggenburger
IPC分类号： G03F7/075 , H01L21/027 , G03C1/492 , G03C1/494
CPC分类号： G03F7/075 , H01L21/0274
摘要： A resist pattern on a substrate is formed using an imageable resist layer on the surface of a substrate. The imageable resist layer comprises a silicon-incorporated polystyrene-diene block copolymer having a silicon weight percent of at least about 5 percent. The imageable layer is prepared by reacting a polystyrene-diene block copolymer with a silicon-containing compound in the presence of a platinum catalyst. In a preferred embodiment, the poly(styrene)-diene block copolymers are hydrosilylated by hydrosiloxanes using a platinum-divinyl tetramethyl disiloxane catalyst.
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公开(公告)号：US20130089984A1
公开(公告)日：2013-04-11
申请号：US13267198
申请日：2011-10-06
申请人： Sudharshanan Raghunathan , Sivananda Kanakasabapathy , Ryan O. Jung , Allen H. Gabor , Sean D. Burns , Erin Catherine Mclellan
发明人： Sudharshanan Raghunathan , Sivananda Kanakasabapathy , Ryan O. Jung , Allen H. Gabor , Sean D. Burns , Erin Catherine Mclellan
IPC分类号： H01L21/311
CPC分类号： H01L21/0338 , H01L21/0337
摘要： Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
摘要翻译： 本发明的实施例提供了一种在具有多个关键尺寸的侧壁图像转印工艺中形成半导体器件的方法。 该方法包括在多个心轴上形成多层介质层，多层介质层具有覆盖多个心轴的多个区域，多层介质层的多个区域具有不同的厚度; 通过施加定向蚀刻工艺将多层电介质层的多个区域蚀刻成间隔物，间隔物形成在多个心轴的侧壁旁边，并且具有对应于多个区域的多个区域的不同厚度的不同宽度 电介质层; 去除间隔件之间的多个心轴; 并将间隔物的底部图像转移到间隔物下面的一个或多个层中。
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公开(公告)号：US20130041494A1
公开(公告)日：2013-02-14
申请号：US13204955
申请日：2011-08-08
申请人： Christopher P. Ausschnitt , Timothy A. Brunner , Allen H. Gabor , Oleg Gluschenkov , Vinayan C. Menon
发明人： Christopher P. Ausschnitt , Timothy A. Brunner , Allen H. Gabor , Oleg Gluschenkov , Vinayan C. Menon
IPC分类号： G06F19/00
CPC分类号： G05B19/401 , G05B2219/2602 , G05B2219/45031
摘要： Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.
摘要翻译： 通过在一个或多个处理步骤之前和之后的光刻处理步骤中测量衬底对准数据来确定由于一个或多个处理步骤导致的衬底的变形。 通过将计算的对准数据差异与在数据库中累积的先前数据进行比较来识别对准数据差异中的任何异常模式。 通过将异常模式与先前识别的针对对准数据差异的工具特定模式进行比较，可以识别引入异常模式和/或异常处理性质的处理步骤，并且可以采取适当的过程控制措施来纠正任何异常 在所识别的处理步骤中。
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