公开(公告)号：US20240074174A1

公开(公告)日：2024-02-29

申请号：US17952322

申请日：2022-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  CHI REN

IPC: H01L27/11521 ,  H01L27/11519 ,  H01L27/11539

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11539

Abstract: A memory device includes a semiconductor substrate, isolation structures, an erase gate, and floating gates. The isolation structures are disposed in the semiconductor substrate. Active regions separated from one another are defined in the semiconductor substrate by the isolation structures, and each of the active regions is elongated in a first direction. The erase gate is disposed on the semiconductor substrate and elongated in a second direction. The erase gate is disposed on the active regions and the isolation structures, and the erase gate is partly disposed in a recess within each of the isolation structures. The floating gates are disposed on the semiconductor substrate. The floating gates are arranged in the second direction and separated from one another, and each of the floating gates is partly disposed under the erase gate in a vertical direction.

公开(公告)号：US20230380154A1

公开(公告)日：2023-11-23

申请号：US18365243

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

CPC classification number: H10B41/30 ,  H01L29/788 ,  H01L29/518 ,  H01L29/513 ,  H01L29/42328

Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.

公开(公告)号：US20230045722A1

公开(公告)日：2023-02-09

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

公开(公告)号：US20230029468A1

公开(公告)日：2023-02-02

申请号：US17510371

申请日：2021-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

公开(公告)号：US10825522B2

公开(公告)日：2020-11-03

申请号：US16173406

申请日：2018-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US10332884B2

公开(公告)日：2019-06-25

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  Jianjun Yang ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Weichang Liu ,  Shen-De Wang ,  Kok Wun Tan

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US20190131302A1

公开(公告)日：2019-05-02

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  JIANJUN YANG ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  WEICHANG LIU ,  Shen-De Wang ,  KOK WUN TAN

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L27/0924 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US10090465B2

公开(公告)日：2018-10-02

申请号：US15359975

申请日：2016-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00

Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

公开(公告)号：US20180205013A1

公开(公告)日：2018-07-19

申请号：US15441261

申请日：2017-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.

公开(公告)号：US20180047842A1

公开(公告)日：2018-02-15

申请号：US15234525

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Shen-De Wang

IPC: H01L29/788 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115 ,  H01L29/06

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66545

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.