公开(公告)号：US20140346645A1

公开(公告)日：2014-11-27

申请号：US13900565

申请日：2013-05-23

Applicant: United Microelectronics Corp.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Abstract translation: 透硅通孔包括基底和导电塞。 基板在一侧具有孔。 导电插头设置在孔中，导电插头具有从侧面突出的上部，其中上部具有顶部和底部，并且顶部比底部更细。 此外，还提供了通过硅通孔形成的贯穿硅通孔工艺，其包括以下步骤。 从一侧在基板上形成孔。 形成第一导电材料以覆盖孔和侧面。 形成图案化的光致抗蚀剂以覆盖侧面但暴露孔。 在暴露的第一导电材料上形成第二导电材料。 去除图案化的光致抗蚀剂。 去除侧面上的第一导电材料以在孔中形成导电塞。

公开(公告)号：US20140203394A1

公开(公告)日：2014-07-24

申请号：US13747492

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L23/538

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US12068234B2

公开(公告)日：2024-08-20

申请号：US18200580

申请日：2023-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L27/08 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L27/01 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16113 ,  H01L2224/16147

Abstract: A semiconductor structure includes an interposer substrate, an electronic device formed in a device region of the interposer substrate, a guard ring formed in the interposer substrate and surrounding the device region, a first redistribution layer on an upper surface of the interposer substrate and covering the device region and the guard ring, and a chip disposed on the first redistribution layer and overlapping the device region.

公开(公告)号：US20230290719A1

公开(公告)日：2023-09-14

申请号：US18200580

申请日：2023-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/48 ,  H01L27/01 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L23/642 ,  H01L23/481 ,  H01L21/486 ,  H01L27/01 ,  H01L21/76898 ,  H01L2224/16147 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16113

Abstract: A semiconductor structure includes an interposer substrate, an electronic device formed in a device region of the interposer substrate, a guard ring formed in the interposer substrate and surrounding the device region, a first redistribution layer on an upper surface of the interposer substrate and covering the device region and the guard ring, and a chip disposed on the first redistribution layer and overlapping the device region.

公开(公告)号：US20220384376A1

公开(公告)日：2022-12-01

申请号：US17880691

申请日：2022-08-04

Applicant: United Microelectronics Corp.

Inventor： Ming-Tse Lin ,  Chung-Hsing Kuo ,  Hui-Ling Chen

IPC: H01L23/00

Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.

公开(公告)号：US20220005775A1

公开(公告)日：2022-01-06

申请号：US16984601

申请日：2020-08-04

Applicant: United Microelectronics Corp.

Inventor： Zhirui Sheng ,  Hui-Ling Chen ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Chien En Hsu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

公开(公告)号：US10340231B2

公开(公告)日：2019-07-02

申请号：US15486521

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US20190027457A1

公开(公告)日：2019-01-24

申请号：US15673223

申请日：2017-08-09

Applicant: United Microelectronics Corp.

Inventor： Ming-Tse Lin

IPC: H01L23/00 ,  H01L25/065 ,  H05K3/46

Abstract: A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.

公开(公告)号：US20180269167A1

公开(公告)日：2018-09-20

申请号：US15486521

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/645 ,  H01L21/568 ,  H01L23/3185 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/1431 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30107

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US09978666B2

公开(公告)日：2018-05-22

申请号：US15663679

申请日：2017-07-28

Applicant: United Microelectronics Corp.

Inventor： Kuei-Sheng Wu ,  Ming-Tse Lin

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.