公开(公告)号：US20180012882A1

公开(公告)日：2018-01-11

申请号：US15247134

申请日：2016-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Hou-Jen Chiu ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.

公开(公告)号：US09859271B2

公开(公告)日：2018-01-02

申请号：US15007163

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wei Lee ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/06

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/7436 ,  H01L29/861

Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.

公开(公告)号：US09793258B1

公开(公告)日：2017-10-17

申请号：US15344212

申请日：2016-11-04

Applicant: United Microelectronics Corp.

Inventor： Cheng-Te Lin ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0259 ,  H01L27/0288

Abstract: An electrostatic discharge device includes a substrate. A deep doped well of a first conductive type is disposed in the substrate. A drain doped well of the first conductive type is disposed in the substrate above the deep doped well. An inserted doping well of a second conductive type is disposed in the drain doped well, in contact with the deep doped well. A drain region of the first conductive type is in the drain doped well and above the inserted doping well. An inserted drain of the second conductive type is on the inserted doping well and surrounded by the drain region. A source doped well of the second conductive type is disposed in the substrate, abut the drain doped well. A source region is disposed in the source doped well. A gate structure is disposed on the substrate between the drain region and the source region.

公开(公告)号：US20170213818A1

公开(公告)日：2017-07-27

申请号：US15481444

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

公开(公告)号：US09673189B2

公开(公告)日：2017-06-06

申请号：US14924975

申请日：2015-10-28

Applicant: United Microelectronics Corp.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.

公开(公告)号：US09660072B2

公开(公告)日：2017-05-23

申请号：US14188645

申请日：2014-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided.

公开(公告)号：US09449960B2

公开(公告)日：2016-09-20

申请号：US13937142

申请日：2013-07-08

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L21/70 ,  H01L27/02

CPC classification number: H01L27/0277

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

Abstract translation: 提供一种包括基板，拾取区域，第一MOS器件，第二MOS器件，第一掺杂区域和第二掺杂区域的静电放电（ESD）保护结构。 拾取区域位于基板中。 第一MOS器件具有位于衬底中的第一导电类型的第一漏极区域。 第二MOS器件具有位于衬底中的第一导电类型的第二漏极区域。 第一漏极区域比第二漏极区域更靠近拾取区域。 第二导电类型的第一掺杂区位于第一掺杂区的下方。 第二导电类型的第二掺杂区位于第二掺杂区的下方。 第一掺杂区域的面积和/或掺杂浓度大于第二掺杂区域的面积和/或掺杂浓度。

公开(公告)号：US09368500B2

公开(公告)日：2016-06-14

申请号：US14071670

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/092 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/0925 ,  H01L21/823892 ,  H01L27/0274 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.

Abstract translation: CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。

公开(公告)号：US20160043216A1

公开(公告)日：2016-02-11

申请号：US14454739

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。

公开(公告)号：US20150221634A1

公开(公告)日：2015-08-06

申请号：US14685588

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，形成在衬底中的栅极的相应两侧处的漏极区域和源极区域，形成在漏极区域中的至少第一掺杂区域，以及至少第一 其中形成有第一掺杂区。 源区和漏区包括第一导电类型，第一掺杂区和第一阱包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。