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31.发明授权公开(公告)号：US09721840B2
公开(公告)日：2017-08-01
申请号：US15194577
申请日：2016-06-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ming Lai , Chien-Chung Huang , Yu-Ting Tseng , Ya-Huei Tsai , Yu-Ping Wang
IPC: H01L21/8234 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/66 , H01L21/283 , H01L21/321 , H01L21/3213 , H01L29/51 , H01L29/78
CPC classification number: H01L21/823437 , H01L21/28088 , H01L21/283 , H01L21/3211 , H01L21/32139 , H01L21/823842 , H01L27/092 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7843
Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
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32.发明授权公开(公告)号：US09524968B1
公开(公告)日：2016-12-20
申请号：US14836966
申请日：2015-08-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ming Lai , Ya-Huei Tsai
IPC: H01L21/02 , H01L27/092 , H01L21/8238 , H01L21/28 , H01L21/3213 , H01L29/49 , H01L29/66
CPC classification number: H01L27/092 , H01L21/28088 , H01L21/32134 , H01L21/82345 , H01L21/8238 , H01L21/823842 , H01L27/0922 , H01L29/49 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
Abstract: A fabrication method of semiconductor device having metal gate includes providing a substrate, successively forming a gate insulating layer and a bottom barrier layer on the surface of the substrate, forming a work function layer covering the bottom barrier layer, removing the work function layer, and forming a top barrier layer on the bottom barrier layer to be directly contact with the bottom barrier layer, and forming a metal layer on the top bottom barrier layer.
Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供衬底，在衬底的表面上依次形成栅绝缘层和底阻挡层，形成覆盖底阻挡层的功函数层，去除功函数层，以及 在所述底部阻挡层上形成与所述底部阻挡层直接接触的顶部阻挡层，并且在所述顶部底部阻挡层上形成金属层。
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公开(公告)号：US20160307805A1
公开(公告)日：2016-10-20
申请号：US15194577
申请日：2016-06-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ming Lai , Chien-Chung Huang , Yu-Ting Tseng , Ya-Huei Tsai , Yu-Ping Wang
IPC: H01L21/8234 , H01L21/3213 , H01L21/283 , H01L21/321
CPC classification number: H01L21/823437 , H01L21/28088 , H01L21/283 , H01L21/3211 , H01L21/32139 , H01L21/823842 , H01L27/092 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7843
Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。
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公开(公告)号：US12150313B2
公开(公告)日：2024-11-19
申请号：US18500994
申请日：2023-11-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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公开(公告)号：US12052933B2
公开(公告)日：2024-07-30
申请号：US18132992
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.
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Patent Agency Ranking
公开(公告)号：US11849592B2
公开(公告)日：2023-12-19
申请号：US17888451
申请日：2022-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
CPC classification number: H10B61/00 , G11C11/161 , H01F10/3254 , H01F41/34 , H01L23/528 , H01L23/5226 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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公开(公告)号：US20230157182A1
公开(公告)日：2023-05-18
申请号：US18098091
申请日：2023-01-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , Ya-Huei Tsai , I-Fan Chang , Yu-Ping Wang
CPC classification number: H10N50/80 , H01F10/3254 , H01F41/34 , H10B61/00 , H10N50/01 , G11C11/161
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
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公开(公告)号：US11456331B2
公开(公告)日：2022-09-27
申请号：US16857152
申请日：2020-04-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H01L43/02 , H01L27/22 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H01L43/12 , H01L43/10
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.
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公开(公告)号：US20210225933A1
公开(公告)日：2021-07-22
申请号：US16792271
申请日：2020-02-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
IPC: H01L27/22 , H01L23/528 , H01L43/02
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.
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公开(公告)号：US20210028353A1
公开(公告)日：2021-01-28
申请号：US16554531
申请日：2019-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang
Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.
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