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    Magnetic tunnel junction (MTJ) device
    31.
    发明授权
    Magnetic tunnel junction (MTJ) device 有权

    公开(公告)号：US11271154B2

    公开(公告)日：2022-03-08

    申请号：US16529740

    申请日：2019-08-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Ting-Hsiang Huang ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

    IPC: H01L45/00 ,  H01L43/02 ,  H01L41/297

    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    32.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20210296576A1

    公开(公告)日：2021-09-23

    申请号：US17336295

    申请日：2021-06-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

    IPC: H01L43/12 ,  H01L43/02

    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

    Method for fabricating a semiconductor device
    34.
    发明授权
    Method for fabricating a semiconductor device 有权

    公开(公告)号：US10804138B2

    公开(公告)日：2020-10-13

    申请号：US15712153

    申请日：2017-09-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

    IPC: H01L21/768

    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.

    Method of preventing trench distortion
    35.
    发明授权
    Method of preventing trench distortion 有权

    公开(公告)号：US09741614B1

    公开(公告)日：2017-08-22

    申请号：US15206330

    申请日：2016-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/027

    CPC classification number: H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

    Abstract: A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON layer from top to bottom. At least two mandrels are formed on the SiOC layer. Later, two spacers are formed respectively at two sidewalls of each mandrel. Subsequently, the mandrels are removed. The SiOC layer and the TiN layer are patterned by using the spacers to form numerous recesses. The spacers are then removed. A mask layer with a via pattern is formed to cover the SiOC layer. A via is formed in the dielectric layer by taking the mask layer as a mask. After that, the mask layer is removed. Finally, numerous trenches are formed in the dielectric layer by taking the SiOC layer and the TiN layer as a mask.

    MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    36.
    发明申请
    MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权
    制造半导体结构的制造方法

    公开(公告)号：US20140349476A1

    公开(公告)日：2014-11-27

    申请号：US13902977

    申请日：2013-05-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

    Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露金属栅极的部分 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

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