中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

87 records (took 0.018 seconds)

    Apparatus and Method for Generating a Variable-Frequency Clock
    31.
    发明申请
    Apparatus and Method for Generating a Variable-Frequency Clock 有权
    用于产生可变频率时钟的装置和方法

    公开(公告)号：US20060050602A1

    公开(公告)日：2006-03-09

    申请号：US11162972

    申请日：2005-09-29

    Applicant: Kevin Lin ,  Alex Chang

    Inventor： Kevin Lin ,  Alex Chang

    IPC: G11C8/00

    CPC classification number: G06F13/4234

    Abstract: Apparatus and method for generating a variable-frequency clock is disclosed. A control state machine defines various commands and generates corresponding control signals. A variable-frequency clock generator then outputs the variable-frequency clock that has a specific pattern corresponding with the respective command, where the variable-frequency clock is constructed with a first clock and a second clock having a frequency different from the first clock. A control signals generator accordingly outputs the control signals that are also constructed with the first clock and the second clock.

    Abstract translation: 公开了一种用于产生可变频率时钟的装置和方法。 控制状态机定义各种命令并产生相应的控制信号。 然后，可变频率时钟发生器输出具有与相应命令对应的特定模式的可变频率时钟，其中可变频率时钟由第一时钟构成，第二时钟具有与第一时钟不同的频率。 控制信号发生器相应地输出也由第一时钟和第二时钟构成的控制信号。

    INTERLEAVED MAPPING METHOD AND APPARATUS FOR ACCESSING MEMORY
    33.
    发明申请
    INTERLEAVED MAPPING METHOD AND APPARATUS FOR ACCESSING MEMORY 审中-公开
    用于访问存储器的交互映射方法和设备

    公开(公告)号：US20050240750A1

    公开(公告)日：2005-10-27

    申请号：US10711843

    申请日：2004-10-08

    Applicant: Kevin Lin

    Inventor： Kevin Lin

    IPC: G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC classification number: G06F12/0607

    Abstract: This invention provides a method for accessing memory. The method includes, generating a block index for a block of data, mapping the block index to a physical address of a memory based on the block index and a number N, wherein N is bank number of the memory, storing the block of data into the memory at the physical address, and repeating from the generating step, wherein the mapping step makes each one of the block indexes map in turns to one physical address located at different banks, and result in any logical adjacent block of data be stored physically at different banks of the memory.

    Abstract translation: 本发明提供一种访问存储器的方法。 该方法包括：产生数据块的块索引，基于块索引将块索引映射到存储器的物理地址，数字N，其中N是存储器的存储区号，将数据块存储到 物理地址处的存储器，并且从生成步骤重复，其中，映射步骤使得每个块索引的每一个映射到位于不同存储体处的一个物理地址，并且导致任何逻辑的相邻数据块物理地存储在 不同银行的记忆。

    Method for forming semiconductor dielectric layer
    34.
    发明授权
    Method for forming semiconductor dielectric layer 失效
    形成半导体电介质层的方法

    公开(公告)号：US06255229B1

    公开(公告)日：2001-07-03

    申请号：US09074780

    申请日：1998-05-08

    Applicant: Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

    Inventor： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

    IPC: H01L21469

    CPC classification number: H01L21/0214 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31625 ,  H01L21/76801

    Abstract: A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

    Abstract translation: 一种形成半导体电介质层的方法，包括以下步骤：提供其上已经形成有多个半导体器件的衬底，然后在衬底上形成第一电介质层。 接下来，在第一介电层上形成氮氧化硅层，最后在氮氧化硅层上形成第二电介质层。

    Simple small feature size bit line formation in DRAM with RTO oxidation
    35.
    发明授权
    Simple small feature size bit line formation in DRAM with RTO oxidation 失效
    具有RTO氧化的DRAM中的简单小特征尺寸位线形成

    公开(公告)号：US6162678A

    公开(公告)日：2000-12-19

    申请号：US188916

    申请日：1998-11-09

    Applicant: Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

    Inventor： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

    IPC: H01L21/768 ,  H01L21/8242

    CPC classification number: H01L21/76885 ,  H01L21/76888 ,  H01L27/10885

    Abstract: A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.

    Abstract translation: 一种用于制造位线的方法能够形成小尺寸的位线。 在该方法中，依次在基板上形成第一电介质层，第一导电层和第二导电层。 第一介质层被暴露，然后分别形成第二导线和第一导线。 第二导线的一部分被清洁液体除去，使得第二导线的特征尺寸小于第一导线的特征尺寸。 通过进行热处理，在第二导线和第一导线上形成氧化物层。 第二导线的特征尺寸近似等于第一导线的特征尺寸。

    Patterning methods for stretchable structures
    40.
    发明授权
    Patterning methods for stretchable structures 有权
    可拉伸结构的图案化方法

    公开(公告)号：US08187795B2

    公开(公告)日：2012-05-29

    申请号：US12331131

    申请日：2008-12-09

    Applicant: Kanti Jain ,  Kevin Lin

    Inventor： Kanti Jain ,  Kevin Lin

    IPC: G03F7/00 ,  G03F7/20 ,  G01B7/16 ,  G01P15/125

    CPC classification number: H05K1/0283 ,  B23K26/40 ,  B23K2103/172 ,  B81B2201/0292 ,  B81B2203/0109 ,  B81B2207/07 ,  B81C1/0019 ,  H05K3/0032 ,  H05K3/007 ,  H05K2201/09109 ,  H05K2203/0554 ,  H05K2203/308

    Abstract: Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser ablation patterning methods utilized herein allow for efficient manufacture of large area (e.g., up to 1 mm2 or greater or 1 m2 or greater) stretchable and/or flexible electronic devices, for example manufacturing methods permitting a reduced number of steps. The techniques described herein further provide for improved heterogeneous integration of components within an electronic device, for example components having improved alignment and/or relative positioning within an electronic device. Also described herein are flexible and/or stretchable electronic devices, such as interconnects, sensors and actuators.

    Abstract translation: 这里描述了使用激光烧蚀图案化方法制造可拉伸和/或柔性电子器件的处理技术。 本文使用的激光烧蚀图案化方法允许有效地制造大面积（例如，高达1mm 2或更大或1m 2或更大）的可拉伸和/或柔性电子器件，例如允许减少步数的制造方法。 本文描述的技术进一步提供了改进的电子设备内的组件的异构集成，例如具有电子设备内的改进的对准和/或相对定位的组件。 本文还描述了柔性和/或可拉伸的电子设备，例如互连，传感器和致动器。

Patent Agency Ranking