公开(公告)号：US20120191401A1

公开(公告)日：2012-07-26

申请号：US13439188

申请日：2012-04-04

申请人： CHANDRAMOULI VISWESWARIAH ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： CHANDRAMOULI VISWESWARIAH ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F19/00

CPC分类号： G01R31/318328 ,  G01R31/318342

摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。

公开(公告)号：US20120124535A1

公开(公告)日：2012-05-17

申请号：US12946950

申请日：2010-11-16

申请人： Jinjun Xiong ,  Vladimir Zolotov

发明人： Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G01R31/31718

摘要： At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.

摘要翻译： 针对要优化制造芯片测试的集成电路芯片设计识别至少一个目标度量。 还针对要优化制造芯片测试的集成电路芯片设计识别至少一个替代度量。 使用一般联合概率密度函数来建模所述至少一个目标度量和所述至少一个代理度量之间的关系。 基于通用联合概率密度函数确定芯片配置准则。 芯片配置标准对于根据设计推定制造的给定物理芯片，基于给定物理芯片的至少一个替代度量来确定在制造芯片测试期间是否接受或丢弃给定的物理芯片。

公开(公告)号：US08176462B2

公开(公告)日：2012-05-08

申请号：US12464025

申请日：2009-05-11

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G01R31/318328 ,  G01R31/318342

摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。

公开(公告)号：US08141025B2

公开(公告)日：2012-03-20

申请号：US12354306

申请日：2009-01-15

申请人： Debjit Sinha ,  Eric A. Foreman ,  Peter A. Habitz ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Debjit Sinha ,  Eric A. Foreman ,  Peter A. Habitz ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).

摘要翻译： 一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。 通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。 到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。 混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。

公开(公告)号：US20100162064A1

公开(公告)日：2010-06-24

申请号：US12340072

申请日：2008-12-19

申请人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/2882

摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.

摘要翻译： 在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。 用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试 将会失败，计算基本上确保路径组满足N和M要求并输出用于选择路径集合的度量的度量。

公开(公告)号：US20100088658A1

公开(公告)日：2010-04-08

申请号：US12244512

申请日：2008-10-02

申请人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.

摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。

公开(公告)号：US20090119629A1

公开(公告)日：2009-05-07

申请号：US11934146

申请日：2007-11-02

申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F11/24 ,  G01R31/31835

摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

公开(公告)号：US07480880B2

公开(公告)日：2009-01-20

申请号：US11358622

申请日：2006-02-21

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/509 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/10 ,  G06F2217/12 ,  Y02P90/265

摘要： The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit, the method comprising: conducting a statistical timing analysis; expressing a statistical circuit delay in terms of a delay of the edge; and computing a gradient of the statistical circuit delay with respect to parameters of the delay of the edge.

摘要翻译： 本发明提供了一种方法，系统和程序产品，用于相对于电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度。 本发明的第一方面提供了一种用于根据电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度的方法，所述方法包括：执行统计时序分析; 根据边缘的延迟表示统计电路延迟; 以及计算相对于边缘的延迟的参数的统计电路延迟的梯度。

公开(公告)号：US20070143722A1

公开(公告)日：2007-06-21

申请号：US11303792

申请日：2005-12-16

申请人： Natesan Venkateswaran ,  Chandramouli Viswewariah ,  JinJun Xiong ,  Vladimir Zolotov

发明人： Natesan Venkateswaran ,  Chandramouli Viswewariah ,  JinJun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge of interest, defining a cutset that divides the timing graph into a plurality of parts, determining an edge slack for each edge in the cutset, computing a statistical maximum of all edge slacks in the cutset, and inferring edge criticality probabilities of each edge from the statistical maximum. A system for determining criticality probability of an edge of a timing graph of a circuit is also described.

摘要翻译： 描述了用于确定电路的时序图的边缘的临界概率的方法。 该方法包括形成对应于正在定时的电路的有向非循环时序图，对于感兴趣的每个边缘执行电路的统计定时，定义将定时图分成多个部分的切片，确定每个边缘的边缘松弛 在切片中，计算切片中所有边缘松弛的统计最大值，并从统计最大值推断每个边缘的边缘关键概率。 还描述了用于确定电路的时序图的边缘的关键概率的系统。

公开(公告)号：US08571825B2

公开(公告)日：2013-10-29

申请号：US13617749

申请日：2012-09-14

申请人： Peter Anton Habitz ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Peter Anton Habitz ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G01R31/3181 ,  G06F11/30

CPC分类号： G01R31/31718 ,  G01R31/31725 ,  G06F17/5031 ,  G06F2217/84

摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。