公开(公告)号：US09559669B1

公开(公告)日：2017-01-31

申请号：US14728741

申请日：2015-06-02

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K3/037 ,  H03K5/05 ,  H03K5/15046

Abstract: A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse generator. A method of generating clock signals enabling the latching of data is also described.

Abstract translation: 描述用于产生能够锁存数据的时钟信号的电路。 该电路包括一个脉冲发生器，它被耦合以在输入端接收一个输入时钟信号，并在输出端产生一个输出时钟信号; 耦合以接收所述输出时钟信号的锁存电路; 以及耦合以接收反馈信号的脉冲整形电路; 其中输出时钟信号的脉冲宽度由耦合到脉冲发生器的反馈信号和输入信号确定。 还描述了产生能够锁定数据的时钟信号的方法。

公开(公告)号：US09438244B2

公开(公告)日：2016-09-06

申请号：US14526192

申请日：2014-10-28

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood ,  Brian C. Gaide ,  Steven P. Young

IPC: G05F1/10 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17784 ,  H03K19/0008 ,  H03K19/0016

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract translation: 用于控制集成电路内的电力的电路包括多个电路块; 在集成电路内布线的全局控制信号; 和多个功率控制块。 每个功率控制块耦合到多个电路块的相应电路块，并且具有耦合以接收参考电压的第一输入和耦合以接收全局控制信号的第二输入。 对于每个电路块，全局控制信号使得参考电压与对应的电路块的耦合。 还公开了一种控制集成电路内的功率的方法。

公开(公告)号：US09007110B1

公开(公告)日：2015-04-14

申请号：US13936597

申请日：2013-07-08

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide

IPC: H03K3/017

CPC classification number: H03K3/02335 ,  H03K3/02332

Abstract: A register circuit adapted to store data is described. The register circuit comprises a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input; and a delay element coupled to the master-slave flip flop, the delay element receiving a reference clock signal and generating a slave clock signal the slave clock signal which is delayed relative to a master clock signal. A method of storing data in a register circuit is also described.

Abstract translation: 描述适于存储数据的寄存器电路。 寄存器电路包括主从触发器，其耦合以在输入处接收由主从触发器存储的数据; 以及耦合到所述主从触发器的延迟元件，所述延迟元件接收参考时钟信号并且产生从时钟信号，所述从时钟信号相对于主时钟信号被延迟。 还描述了将数据存储在寄存器电路中的方法。

公开(公告)号：US12235671B2

公开(公告)日：2025-02-25

申请号：US18199838

申请日：2023-05-19

Applicant: XILINX, INC.

Inventor： Brian C. Gaide

IPC: G06F1/00 ,  G06F1/10

Abstract: An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.

公开(公告)号：US12154617B2

公开(公告)日：2024-11-26

申请号：US17950022

申请日：2022-09-21

Applicant: XILINX, INC.

Inventor： Brian C. Gaide

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4093

Abstract: A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.

公开(公告)号：US11901300B2

公开(公告)日：2024-02-13

申请号：US17677899

申请日：2022-02-22

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Brian C. Gaide

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/06 ,  H01L25/18 ,  H01L2224/0612

Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.

公开(公告)号：US20230291405A1

公开(公告)日：2023-09-14

申请号：US18320168

申请日：2023-05-18

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/17712

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

公开(公告)号：US11451230B2

公开(公告)日：2022-09-20

申请号：US16857090

申请日：2020-04-23

Applicant: XILINX, INC.

Inventor： Steven P. Young ,  Brian C. Gaide

IPC: H03K19/17748 ,  H03K19/17736 ,  G06F1/10 ,  G06F8/40

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US09859896B1

公开(公告)日：2018-01-02

申请号：US14851601

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young ,  Eric F. Dellinger

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17728

Abstract: In an example, a programmable integrated circuit (IC) includes external contacts configured to interface with a substrate and a plurality of configurable logic elements (CLEs) distributed across a programmable fabric. The programmable IC further includes interconnect circuits disposed between the plurality of CLEs and the external contacts. A plurality of the interconnect circuits is disposed in the plurality of CLEs.

公开(公告)号：US09143122B1

公开(公告)日：2015-09-22

申请号：US14268671

申请日：2014-05-02

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide

IPC: H03K5/159 ,  H03K5/00

CPC classification number: H03K5/159 ,  G06F1/10 ,  H03K2005/00078

Abstract: A system includes: an initial clock region; a first adjacent clock region adjacent to the initial clock region; a spine coupled to receive a clock signal from a clock; and a first phase detector coupled to detect a difference in phase between the initial clock region and the first adjacent clock region. The initial clock region comprises an initial delay element coupled to the spine and to the first phase detector.

Abstract translation: 系统包括：初始时钟区域; 与初始时钟区域相邻的第一相邻时钟区域; 一个被连接以从时钟接收时钟信号的脊柱; 以及耦合以检测初始时钟区域和第一相邻时钟区域之间的相位差的第一相位检测器。 初始时钟区域包括耦合到脊柱和第一相位检测器的初始延迟元件。