公开(公告)号：US06426543B1

公开(公告)日：2002-07-30

申请号：US09717038

申请日：2000-11-22

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L2900

CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜包括具有第一宽度并且在大致垂直于掩埋氧化膜的表面的方向上延伸的第一部分和具有小于第一宽度的第二宽度的第二部分并且连续地形成在第一部分下方， 大致垂直于埋入氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

公开(公告)号：US06727572B2

公开(公告)日：2004-04-27

申请号：US10340664

申请日：2003-01-13

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L2900

CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜包括具有第一宽度并且在大致垂直于掩埋氧化膜的表面的方向上延伸的第一部分和具有小于第一宽度的第二宽度的第二部分并且连续地形成在第一部分下方， 大致垂直于埋入氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

公开(公告)号：US06310377B1

公开(公告)日：2001-10-30

申请号：US09134896

申请日：1998-08-17

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76291 ,  H01L27/11807 ,  H01L27/1203

摘要： FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。 因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。

公开(公告)号：US5808341A

公开(公告)日：1998-09-15

申请号：US747933

申请日：1996-11-12

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L21/762 ,  H01L21/82 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L27/11807 ,  H01L27/1203 ,  H01L21/76281 ,  H01L21/76291

摘要： FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b），LOCOS隔离场（11c，11d），FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i） 这个命令。 因此，可以提供主布局，其中将具有被提供固定电位的体的SOI晶体管和具有不具有固定电位的体的SOI晶体管混合。

公开(公告)号：US20070032001A1

公开(公告)日：2007-02-08

申请号：US11543213

申请日：2006-10-05

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US20060186474A1

公开(公告)日：2006-08-24

申请号：US11408181

申请日：2006-04-21

申请人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

摘要： It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “−” functions as a gate electrode of an original MOS transistor.

摘要翻译： 本发明的目的是提供具有SOI结构的半导体器件，其中可以以高稳定性固定由部分隔离区隔离的元件形成区域中的体区的电位。 在由部分氧化膜（31）隔离的元件形成区域中形成包括源极区（51），漏极区（61）和H栅电极（71）的MOS晶体管。 H栅电极（71）将从栅极宽度W方向形成的主体区域（13）与漏极区域（61）和源极区域（51）的源极区域（51）和漏极区域（61）相邻地隔离 ）通过“I”横向（图中的垂直方向），中心“ - ”用作原始MOS晶体管的栅电极。

公开(公告)号：US07005705B2

公开(公告)日：2006-02-28

申请号：US10261665

申请日：2002-10-02

申请人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

公开(公告)号：US07494883B2

公开(公告)日：2009-02-24

申请号：US11543213

申请日：2006-10-05

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60〜120keV，通道阻挡层的密度为1×10 17〜1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US20050101091A1

公开(公告)日：2005-05-12

申请号：US11011655

申请日：2004-12-15

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8242 ,  H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US06875663B2

公开(公告)日：2005-04-05

申请号：US10237022

申请日：2002-09-09

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。