公开(公告)号：US4154491A

公开(公告)日：1979-05-15

申请号：US787686

申请日：1977-04-14

申请人： William J. Derner ,  James R. Elliott

发明人： William J. Derner ,  James R. Elliott

IPC分类号： F16C19/26 ,  F16C33/46 ,  F16C43/04

CPC分类号： F16C33/4623 ,  F16C19/26 ,  F16C43/04

摘要： A bearing assembly retainer ring has pockets for holding cylindrical rollers in arcuately spaced relationship about a central axis of the retainer ring. Each pocket has two end faces that are spaced axially of the retainer ring and two side faces that are spaced laterally of the axial spacing between the two end faces. The pocket extends radially through inner and outer peripheral edges of the retainer ring to receive a roller therein having a diameter which is greater than the radial span of the pocket end faces so that the roller extends beyond the inner and outer peripheral edges of the retainer ring. The axial spacing between the pocket end faces is slightly greater than the axial length of the roller to provide restricted clearances between the ends of the roller and the end faces of the pocket when the roller is centered within the pocket. Chamfers are provided on the end faces of the pockets at the inner and outer peripheral edges thereof. These chamfers enable the roller to pivot within the pocket from a position wherein the roller is aligned axially between the pocket end faces to a cocked position wherein both end faces of the pocket contact the roller and/or the side faces of the pocket contact the roller to resist further pivotal movement.

摘要翻译： 轴承组件保持环具有用于围绕保持环的中心轴线以弓形间隔的关系保持圆柱形辊的凹槽。 每个凹槽具有两个端面，该端面在保持环的轴向间隔开，并且两个侧面与两个端面之间的轴向间隔横向隔开。 口袋径向延伸通过保持环的内周边缘和外周边缘，以容纳其中具有大于口袋端面的径向跨度的直径的辊，使得辊延伸超过保持环的内外边缘 。 袋体端面之间的轴向间距略大于辊子的轴向长度，以便当辊子在口袋内居中时，在滚筒端部和袋口端面之间提供有限的间隙。 在其内周和外周缘处，在凹穴的端面设置有倒角。 这些倒角使得辊能够在凹穴内从一个位置轴向枢转，其中辊子位于口袋端面之间的轴向对准位置，其中口袋的两个端面接触辊子和/或口袋的侧面接触辊子 抵抗进一步的关键运动。

公开(公告)号：US07342290B2

公开(公告)日：2008-03-11

申请号：US10981232

申请日：2004-11-04

申请人： Jay S. Burnham ,  James R. Elliott ,  Kenneth R. Gault ,  Mousa H. Ishaq ,  Steven M. Shank ,  Mary A. St. Lawrence

发明人： Jay S. Burnham ,  James R. Elliott ,  Kenneth R. Gault ,  Mousa H. Ishaq ,  Steven M. Shank ,  Mary A. St. Lawrence

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/28194 ,  H01L21/02046 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S257/913

摘要： A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

摘要翻译： 提供了用于大大减少或消除随后的多晶硅沉积期间形成的金属污染物的双层电介质结构。 双层电介质结构包括位于底表面区域顶部富含氯的上表面区域。 富含氯的上表面区域除去在随后形成多晶硅层期间存在于结构顶部的金属污染物。 还提供了形成双层结构的方法。

公开(公告)号：US06838396B2

公开(公告)日：2005-01-04

申请号：US10249292

申请日：2003-03-28

申请人： Jay S. Burnham ,  James R. Elliott ,  Kenneth R. Gault ,  Mousa H. Ishaq ,  Steven M. Shank ,  Mary A. St. Lawrence

发明人： Jay S. Burnham ,  James R. Elliott ,  Kenneth R. Gault ,  Mousa H. Ishaq ,  Steven M. Shank ,  Mary A. St. Lawrence

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28194 ,  H01L21/02046 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S257/913

摘要： A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

摘要翻译： 提供了用于大大减少或消除随后的多晶硅沉积期间形成的金属污染物的双层电介质结构。 双层电介质结构包括位于底表面区域顶部富含氯的上表面区域。 富含氯的上表面区域除去在随后形成多晶硅层期间存在于结构顶部的金属污染物。 还提供了形成双层结构的方法。

公开(公告)号：US20100032796A1

公开(公告)日：2010-02-11

申请号：US12187419

申请日：2008-08-07

申请人： Brennan J. Brown ,  James R. Elliott ,  Alvin A. Joseph ,  Edward J. Nowak

发明人： Brennan J. Brown ,  James R. Elliott ,  Alvin A. Joseph ,  Edward J. Nowak

IPC分类号： H01L23/58 ,  G06F17/50

CPC分类号： H01L23/66 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/585 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

公开(公告)号：US07927963B2

公开(公告)日：2011-04-19

申请号：US12187415

申请日：2008-08-07

申请人： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

发明人： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76283 ,  H01L21/764 ,  H01L27/12

摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

摘要翻译： 公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。 这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。 具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。 沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。 衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。 可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

公开(公告)号：US07804151B2

公开(公告)日：2010-09-28

申请号：US12187419

申请日：2008-08-07

申请人： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

发明人： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

IPC分类号： H01L23/58

CPC分类号： H01L23/66 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/585 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

摘要翻译： 公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。 这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。 具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。 沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。 衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。 可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

公开(公告)号：US20100035403A1

公开(公告)日：2010-02-11

申请号：US12187415

申请日：2008-08-07

申请人： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

发明人： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76283 ,  H01L21/764 ,  H01L27/12

摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

摘要翻译： 公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。 这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。 具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。 沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。 衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。 可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

公开(公告)号：US20080116493A1

公开(公告)日：2008-05-22

申请号：US11560893

申请日：2006-11-17

申请人： James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart ,  Dale W. Martin

发明人： James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart ,  Dale W. Martin

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.

摘要翻译： 半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。 多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。 第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。 通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。 因此确保了多层间隔层的尺寸完整性和分层避免。