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133 条记录 (耗时 0.043 秒)

    Semiconductor device and method of manufacturing the same
    31.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08350336B2

    公开(公告)日：2013-01-08

    申请号：US12943470

    申请日：2010-11-10

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/823412 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/0688 ,  H01L29/78

    摘要： In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.

    摘要翻译： 在半导体器件及其制造方法中，从衬底的单元区域去除第一绝缘层，并且通过激光诱导外延生长（LEG）工艺在第一区域上形成第一有源图案。 第一绝缘层的残余物被动地形成在第一区域上的第一器件隔离图案中。 从衬底的第二区域去除第一绝缘层，并通过SEG工艺在衬底的第二区域上形成半导体层。 将第二区域上的半导体层图案化为包括凹部的第二有源图案，并且凹陷部分中的第二绝缘图案形成第二区域上的第二器件隔离图案。 因此，减轻或消除了SEG过程中的LEG过程中的晶粒缺陷和晶格缺陷。

    Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions
    33.
    发明申请
    Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions 有权
    制造具有高的源极/漏极区域的凹槽的MOS晶体管的方法

    公开(公告)号：US20120034746A1

    公开(公告)日：2012-02-09

    申请号：US13241311

    申请日：2011-09-23

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Vertical-type semiconductor device
    35.
    发明授权
    Vertical-type semiconductor device 有权
    垂直型半导体器件

    公开(公告)号：US07960780B2

    公开(公告)日：2011-06-14

    申请号：US12478081

    申请日：2009-06-04

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L29/772 ,  H01L21/8242

    CPC分类号： H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

    摘要： In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

    摘要翻译： 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

    Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions
    37.
    发明申请
    Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions 有权
    制造具有高的源极/漏极区域的凹陷的MOS晶体管的方法

    公开(公告)号：US20100041201A1

    公开(公告)日：2010-02-18

    申请号：US12582073

    申请日：2009-10-20

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Fin field effect transistors having capping insulation layers
    38.
    发明授权
    Fin field effect transistors having capping insulation layers 有权
    Fin场效应晶体管具有封盖绝缘层

    公开(公告)号：US07642589B2

    公开(公告)日：2010-01-05

    申请号：US11433942

    申请日：2006-05-15

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

    摘要： A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

    摘要翻译： 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。

    Vertical-type non-volatile memory devices
    39.
    发明申请
    Vertical-type non-volatile memory devices 有权
    垂直型非易失性存储器件

    公开(公告)号：US20090121271A1

    公开(公告)日：2009-05-14

    申请号：US12290742

    申请日：2008-11-03

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L29/788 ,  H01L21/3205

    CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

    摘要： In a semiconductor device, and a method of manufacturing thereof, the device comprises a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案与垂直沟道之间，使栅极图案与垂直沟道绝缘 。