公开(公告)号：US08551759B2

公开(公告)日：2013-10-08

申请号：US11686506

申请日：2007-03-15

申请人： Jung-hwan Hah ,  Sung-min Chi ,  Kyoung-seon Kim ,  Won-sun Kim ,  Han-ku Cho ,  Sang-jun Choi ,  Man-hyoung Ryoo

发明人： Jung-hwan Hah ,  Sung-min Chi ,  Kyoung-seon Kim ,  Won-sun Kim ,  Han-ku Cho ,  Sang-jun Choi ,  Man-hyoung Ryoo

IPC分类号： C12M1/00 ,  C12M1/34 ,  C12Q1/68 ,  G01N33/53 ,  G01N33/551 ,  G01N33/552 ,  G01N33/545 ,  C07H21/02

CPC分类号： C12Q1/6834 ,  C12Q2563/155

摘要： An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.

摘要翻译： 提供了具有改善的反应产率的低聚物探针阵列。 低聚物探针阵列包括基底，基底上的固定层，与固定层的表面耦合的多个纳米颗粒以及与纳米颗粒表面结合的多个低聚物探针。

公开(公告)号：US07795099B2

公开(公告)日：2010-09-14

申请号：US11979748

申请日：2007-11-08

申请人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

发明人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

IPC分类号： H01L21/762

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

摘要翻译： 具有翅片型有源区的半导体器件包括沿着半导体器件的栅电极的方向设置的多个有源区，第一器件隔离层和凹陷的第二器件隔离层。 凹陷的第二器件隔离层和第一器件隔离层设置在栅电极的垂直方向上。 第一器件隔离层和多个有源区交替地设置在多个有源区的第一方向上。

公开(公告)号：US07378196B2

公开(公告)日：2008-05-27

申请号：US10982813

申请日：2004-11-08

申请人： Byeong-Soo Kim ,  Han-ku Cho

发明人： Byeong-Soo Kim ,  Han-ku Cho

IPC分类号： G03F1/00

CPC分类号： G03F1/34 ,  G03F1/29 ,  G03F1/36 ,  G03F7/70441

摘要： A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light at the boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in an isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.

摘要翻译： 掩模校正光学邻近效应（OPE）。 在掩模基板上形成具有相边效应的虚设图案。 相位效应通过透射光降低两个透射区域的边界处的光强度，具有相位差。 然后可以使用相缘效应在光刻工艺中形成图案。 可以通过在掩模的隔离图案区域中形成虚设图案并使孤立图案的衍射图案与致密图案相同，从而可以减小在晶片上形成的“隔离”和“密集”图案之间的差异，由此 提高总焦距。 因为在透射光的相位为0°的第一区域和透射光的相位为180°的第二区域之间的边界处的光的强度例如光致抗蚀剂层不被光敏化 。

公开(公告)号：US20080038732A1

公开(公告)日：2008-02-14

申请号：US11686506

申请日：2007-03-15

申请人： Jung-Hwan Hah ,  Sung-min Chi ,  Kyoung-seon Kim ,  Won-sun Kim ,  Han-ku Cho ,  Sang-jun Choi ,  Man-hyoung Ryoo

发明人： Jung-Hwan Hah ,  Sung-min Chi ,  Kyoung-seon Kim ,  Won-sun Kim ,  Han-ku Cho ,  Sang-jun Choi ,  Man-hyoung Ryoo

IPC分类号： C12Q1/68 ,  C07H21/00

CPC分类号： C12Q1/6834 ,  C12Q2563/155

摘要： An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.

摘要翻译： 提供了具有改善的反应产率的低聚物探针阵列。 低聚物探针阵列包括基底，基底上的固定层，与固定层的表面耦合的多个纳米颗粒以及与纳米颗粒的表面耦合的多个低聚物探针。

公开(公告)号：US07205241B2

公开(公告)日：2007-04-17

申请号：US10731931

申请日：2003-12-10

申请人： Chang-min Park ,  Jung-hyeon Lee ,  Han-ku Cho ,  Joon-soo Park

发明人： Chang-min Park ,  Jung-hyeon Lee ,  Han-ku Cho ,  Joon-soo Park

IPC分类号： H01L21/302

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/91 ,  Y10S438/942

摘要： Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

摘要翻译： 提供了制造具有沿位线方向延伸的接触体以增加接触体与存储电极之间的接触面积的半导体器件的方法。 在一个方面，一种方法包括在半导体衬底上形成栅极线，形成第一绝缘层以覆盖栅极线，形成第一接触焊盘和第二接触焊盘，这些接触焊盘和第二接触焊盘通过穿透栅极线与半导体衬底电连接 第一绝缘层。 此外，形成第二绝缘层以覆盖第一接触焊盘和第二接触焊盘，并且位线横跨栅极线形成，并且通过穿透第二绝缘层而电连接到第二接触焊盘。 此外，形成第三绝缘层以覆盖位线，并且被选择性地蚀刻以形成穿过位线并暴露第一接触焊盘的带状开口。

公开(公告)号：US06841801B2

公开(公告)日：2005-01-11

申请号：US10106289

申请日：2002-03-27

申请人： Byeong-Soo Kim ,  Han-ku Cho

发明人： Byeong-Soo Kim ,  Han-ku Cho

IPC分类号： G03F1/00 ,  G03F1/29 ,  G03F1/32 ,  G03F1/34 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F1/80 ,  G03F7/20 ,  H01L21/027 ,  H01L33/00

CPC分类号： G03F1/34 ,  G03F1/29 ,  G03F1/36 ,  G03F7/70441

摘要： A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in a isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.

摘要翻译： 掩模校正光学邻近效应（OPE）。 在掩模基板上形成具有相边效应的虚设图案。 相位效应通过透射光减少两个透射区域的光边界的强度具有相位差。 然后可以使用相缘效应在光刻工艺中形成图案。 可以通过在掩模的隔离图案区域中形成虚拟图案并使隔离图案的衍射图案与致密图案相同，从而可以减小在晶片上形成的“隔离”和“密集”图案之间的差异，由此 提高总焦距。 因为在透射光的相位为0°的第一区域和透射光的相位为180°的第二区域之间的边界处的光的强度例如光致抗蚀剂层不被光敏化 。

公开(公告)号：US08278221B2

公开(公告)日：2012-10-02

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US08003543B2

公开(公告)日：2011-08-23

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US07604918B2

公开(公告)日：2009-10-20

申请号：US11655977

申请日：2007-01-22

申请人： Sang-jun Choi ,  Han-ku Cho

发明人： Sang-jun Choi ,  Han-ku Cho

IPC分类号： G03F7/039 ,  G03C1/73

CPC分类号： G03F7/0395 ,  C08F220/18 ,  C08F232/08 ,  C08F236/20 ,  G03F7/0397

摘要： A photosensitive polymer for a photoresist and a photoresist composition having the same are provided. The photosensitive polymer for a photoresist includes the repeating unit represented by the formula below: wherein R1 is a C1-C20 hydrocarbon group or a C1-C20 hetero hydrocarbon group including at least one hetero atom selected from the group consisting of nitrogen, fluorine and sulfur.

摘要翻译： 提供了用于光致抗蚀剂的光敏聚合物和具有该光致抗蚀剂组合物的光致抗蚀剂组合物。 用于光致抗蚀剂的光敏聚合物包括由下式表示的重复单元：其中R1是C1-C20烃基或包含至少一个选自氮，氟和硫的杂原子的C1-C20杂烃基 。

公开(公告)号：US20080105931A1

公开(公告)日：2008-05-08

申请号：US11979748

申请日：2007-11-08

申请人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

发明人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

摘要翻译： 具有翅片型有源区的半导体器件包括沿着半导体器件的栅电极的方向设置的多个有源区，第一器件隔离层和凹陷的第二器件隔离层。 凹陷的第二器件隔离层和第一器件隔离层设置在栅电极的垂直方向上。 第一器件隔离层和多个有源区交替地设置在多个有源区的第一方向上。