公开(公告)号：US09013045B2

公开(公告)日：2015-04-21

申请号：US14242562

申请日：2014-04-01

Applicant: Avalanche Technology Inc.

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC: H01L23/522 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L23/5226 ,  H01L27/222 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. In either the first or second embodiments a single layer or a dual layer etch stop layer structure can be deposited over the wafer after the sidewall protection sleeve has been formed and before the inter-layer dielectric (ILD) is deposited.

Abstract translation: 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。 在第一或第二实施例中，在形成侧壁保护套之后并且在沉积层间电介质（ILD）之前，单层或双层蚀刻停止层结构可沉积在晶片之上。

公开(公告)号：US20150102439A1

公开(公告)日：2015-04-16

申请号：US14256192

申请日：2014-04-18

Applicant: Avalanche Technology, Inc.

Inventor： Huadong Gan ,  Yuchen Zhou ,  Yiming Huai ,  Zihui Wang ,  Xiaobin Wang

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/10 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01L27/228 ,  H01L29/66984 ,  H01L43/08

Abstract: The present invention is directed to an MRAM element comprising a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic reference layer structure, which includes a first and a second magnetic reference layers with a tantalum perpendicular enhancement layer interposed therebetween, an insulating tunnel junction layer formed adjacent to the first magnetic reference layer opposite the tantalum perpendicular enhancement layer, and a magnetic free layer formed adjacent to the insulating tunnel junction layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.

Abstract translation: 本发明涉及一种包括多个磁性隧道结（MTJ）存储元件的MRAM元件。 每个存储元件包括磁性参考层结构，其包括第一和第二磁性参考层，其间插入有钽垂直增强层，邻近第一磁性参考层形成的与钽垂直增强层相对的绝缘隧道结层 和与绝缘隧道结层相邻形成的无磁性层。 第一和第二磁性参考层具有基本上垂直于其层平面的第一固定磁化方向。

公开(公告)号：US09009396B2

公开(公告)日：2015-04-14

申请号：US13745686

申请日：2013-01-18

Applicant: Avalanche Technology, Inc.

Inventor： Siamack Nemazie

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7207 ,  Y02D10/13

Abstract: A computer system includes a central processing unit (CPU), a system memory coupled to the CPU and including flash tables, and a physically-addressable solid state disk (SSD) coupled to the CPU. The physically-addressable SSD includes a flash subsystem and a non-volatile memory and is addressable using physical addresses. The flash subsystem includes one or more copies of the flash tables and the non-volatile memory includes updates to the copy of the flash tables. The flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressable SSD, wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption.

Abstract translation: 计算机系统包括中央处理单元（CPU），耦合到CPU并包括闪存表的系统存储器以及耦合到CPU的物理可寻址固态盘（SSD）。 物理可寻址的SSD包括闪存子系统和非易失性存储器，并且可使用物理地址进行寻址。 闪存子系统包括闪存表的一个或多个副本，并且非易失性存储器包括对闪存表副本的更新。 闪存表包括用于将逻辑映射到物理块的表，用于识别物理可寻址SSD中存储的数据的位置，其中闪存表的副本和闪存表的一个或多个副本的更新用于重构 电源中断时闪存表。

公开(公告)号：US08982616B1

公开(公告)日：2015-03-17

申请号：US13685650

申请日：2012-11-26

Applicant: Avalanche Technology, Inc.

Inventor： Rajiv Yadav Ranjan ,  Roger Klas Malmhall ,  Yiming Huai

IPC: G11C11/14 ,  H01L43/02

CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A perpendicular spin transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract translation: 垂直自旋传递转矩磁随机存取存储器（STTMRAM）元件包括具有在一个方向上基本上固定的磁化的固定层和形成在固定层的顶部上的阻挡层和自由层。 自由层具有多个交替的层压体，每个层压体由磁性层和绝缘层制成。 磁性层可切换并形成在阻挡层的顶部。 当在STTMRAM元件上施加双向电流时，自由层能够在写入操作期间相对于固定层的磁化将其磁化转换成平行或反平行状态。 在写入操作期间，层压体的磁性层被铁磁耦合以作为单个区域一起切换，并且固定和自由层的磁化以及层压体的磁性层具有垂直的各向异性。

公开(公告)号：US08971107B2

公开(公告)日：2015-03-03

申请号：US14281873

申请日：2014-05-19

Applicant: Avalanche Technology, Inc.

Inventor： Petro Estakhri ,  Ebrahim Abedifard ,  Frederick Jaffin ,  Siamack Nemazie

IPC: G11C11/14 ,  G11C11/16 ,  G11C8/04 ,  G11C7/10

CPC classification number: G11C11/1673 ,  G11C7/1042 ,  G11C8/04 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1693

Abstract: A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

Abstract translation: 磁存储器系统包括包括多个磁存储器组的磁随机存取存储器（MRAM），并且可操作以在由写命令发起的写操作期间存储数据。 磁存储器系统还包括耦合到MRAM并且包括多个FIFO的先进先出（FIFO）接口设备。每个磁存储器组耦合到多个FIFO中的相应一个，FIFO是 可操作地在每个磁存储体的基础上排队写入命令，并进一步操作以在不使用MRAM时发出排队的写入命令，其中并行写入操作被执行到多个磁存储器组中的至少两个。

公开(公告)号：US08917546B2

公开(公告)日：2014-12-23

申请号：US13625586

申请日：2012-09-24

Applicant: Avalanche Technology, Inc.

Inventor： Ebrahim Abedifard

IPC: G11C11/14 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/5607

Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.

Abstract translation: 写入磁存储器阵列的磁性隧道结（MTJ）的方法包括耦合到MTJ的访问晶体管，用于读取和写入MTJ，其中当MTJ被写入时有时通过切换其磁性取向 从反并联到并行磁取向，耦合到MTJ的一端的位线被提升到Vcc，并且作为Vcc和Vx之和的电压被施加到存取晶体管的栅极，Vx 大约是MTJ相对端的电压。 此外，使用也耦合到SL的写入驱动器的第一晶体管耦合到MTJ的源极线（SL）的电压被调节，使得SL保持足够高于0伏，以避免超过Vgs的超出 Vcc，其中Vgs是存取晶体管的源极电压的栅极。

公开(公告)号：US20140281680A1

公开(公告)日：2014-09-18

申请号：US14217268

申请日：2014-03-17

Applicant: Avalanche Technology, Inc.

Inventor： Siamack NEMAZIE ,  Ravishankar TADEPALLI ,  Mehdi ASNAASHARI

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components.

Abstract translation: 存储器模块包括具有第一接口和第二接口的桥接控制器。 第一接口从主机接收命令和数据，并且第二接口耦合到一个或多个存储器组件。 桥接控制器对存储在一个或多个存储器组件中的数据执行多位错误检测和校正。

公开(公告)号：US20140269041A1

公开(公告)日：2014-09-18

申请号：US14281873

申请日：2014-05-19

Applicant: Avalanche Technology, Inc.

Inventor： Petro Estakhri ,  Ebrahim ABEDIFARD ,  Frederick JAFFIN ,  Siamack NEMAZIE

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/1042 ,  G11C8/04 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1693

Abstract: A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

Abstract translation: 磁存储器系统包括包括多个磁存储器组的磁随机存取存储器（MRAM），并且可操作以在由写命令发起的写操作期间存储数据。 磁存储器系统还包括耦合到MRAM并且包括多个FIFO的先进先出（FIFO）接口设备。每个磁存储器组耦合到多个FIFO中的相应一个，FIFO是 可操作地在每个磁存储体的基础上排队写入命令，并进一步操作以在不使用MRAM时发出排队的写入命令，其中并行写入操作被执行到多个磁存储器组中的至少两个。

公开(公告)号：US08836000B1

公开(公告)日：2014-09-16

申请号：US13891833

申请日：2013-05-10

Applicant: Avalanche Technology, Inc.

Inventor： Tsann Lin

IPC: H01L29/76 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L43/08

Abstract: The invention provides a bottom-type perpendicular magnetic tunnel junction (pMTJ) element with thermally stable amorphous blocking layers for high-density nonvolatile data storage. The first blocking layer, preferably formed of an amorphous nonmagnetic film, blocks a polycrystalline diffusion barrier layer with a body-center-cubic (bcc) texture in order for the keeper and lower reference layers of the bottom-type pMTJ element to freely grow with a face-centered-cubic (fcc) texture, thereby developing strong perpendicular magnetic anisotropy (PMA). The second blocking layer, preferably formed of an amorphous ferromagnetic film, blocks the keeper and lower reference layers of the bottom-type pMTJ element in order for the upper reference, barrier and storage layers of the bottom-type pMTJ element to freely grow with a texture, thereby exhibiting a strong tunneling magnetoresistance (TMR) effect.

Abstract translation: 本发明提供了具有用于高密度非易失性数据存储的热稳定非晶阻挡层的底部型垂直磁隧道结（pMTJ）元件。 优选由非晶非磁性膜形成的第一阻挡层阻挡具有体心立方（bcc）110结构的多晶扩散阻挡层，以使底部型pMTJ元件的保持器和下参考层为 随着面心立方（fcc）<111>纹理自由生长，从而发展出强烈的垂直磁各向异性（PMA）。 优选由非晶铁磁膜形成的第二阻挡层阻挡底部型pMTJ元件的保持器和下参考层，以便底型pMTJ元件的上参考，阻挡层和存储层自由地与 <001>纹理，从而表现出强的隧道磁阻（TMR）效应。

公开(公告)号：US20140252356A1

公开(公告)日：2014-09-11

申请号：US14195473

申请日：2014-03-03

Applicant: Avalanche Technology Inc.

Inventor： Zihui Wang ,  Yuchen Zhou ,  Yiming Huai

IPC: H01L21/66 ,  H01L27/22

CPC classification number: H01L27/222 ,  G01R31/2648 ,  G11C11/16 ,  G11C29/50008 ,  G11C2029/5002 ,  H01L22/34

Abstract: Methods for testing magnetoresistance of test devices with layer stacks, such as MTJs, fabricated on a wafer are described. The test devices can be fabricated along with arrays of similarly structured memory cells on a production wafer to allow in-process testing. The test devices with contact pads at opposite ends of the bottom electrode allow resistance across the bottom electrode to be measured as a surrogate for measuring resistance between the top and bottom electrodes. An MTJ test device according to the invention has a measurable magnetoresistance (MR) between the two contact pads that is a function of the magnetic orientation of the free layer and varies with the length and width of the MTJ strip in each test device. The set of test MTJs can include a selected range of lengths to allow the tunnel magnetoresistance (TMR) and resistance area product (RA) to be estimated or predicted.

Abstract translation: 描述了在晶片上制造的具有层堆叠（例如MTJ）的测试装置的磁阻测试方法。 测试装置可以与生产晶片上的类似结构的存储器单元的阵列一起制造，以允许进行中的测试。 具有在底部电极的相对端的接触焊盘的测试装置允许要测量的底部电极的电阻作为用于测量顶部和底部电极之间的电阻的替代。 根据本发明的MTJ测试装置在两个接触焊盘之间具有可测量的磁阻（MR），其是自由层的磁性取向的函数，并且随每个测试装置中的MTJ条的长度和宽度而变化。 测试MTJ的集合可以包括所选择的长度范围，以允许估计或预测隧道磁阻（TMR）和电阻面积积（RA）。