公开(公告)号：US20080239798A1

公开(公告)日：2008-10-02

申请号：US12000981

申请日：2007-12-19

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078

Abstract: One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal.

Abstract translation: 本发明的一个实施例提供一种补偿电路。 补偿电路包括写入驱动器，距离检测电路，操作元件和辅助写入驱动器。 写入驱动器向写入路径提供写入电流。 距离检测电路耦合到写入路径以检测写入电流已经行进的距离，并且基于该距离输出控制信号。 操作元件耦合到写入路径。 辅助写入驱动器基于控制信号向写入路径提供辅助电流。

公开(公告)号：US20080237562A1

公开(公告)日：2008-10-02

申请号：US11955293

申请日：2007-12-12

Applicant: Yi-Chan Chen ,  Chih-Wei Chen ,  Hong-Hui Hsu ,  Chien-Min Lee

Inventor： Yi-Chan Chen ,  Chih-Wei Chen ,  Hong-Hui Hsu ,  Chien-Min Lee

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSixNy) is formed by a self-aligned silicidizing and nitrifying process. Self-aligned silicidization can be achieved by nitrogen ion implantation or nitrogen-containing plasma treatment. The resistance of the heating element can be regulated by adjusting the content of nitrogen or degree of nitrification.

Abstract translation: 相变存储器件及其制造方法。 相变存储器件包括具有导电部分和相对较高电阻部分的堆叠加热元件，其中相对较高的电阻部分包括含氮金属硅化物部分。 通过自对准的硅化和硝化工艺形成诸如高阻值含氮金属硅化物（MSi x N N y）的加热层叠元件。 自对准硅化可以通过氮离子注入或含氮等离子体处理来实现。 可以通过调节氮的含量或硝化程度来调节加热元件的电阻。

公开(公告)号：US20080233706A1

公开(公告)日：2008-09-25

申请号：US12111980

申请日：2008-04-30

Applicant: Jih-Wen Chou ,  Yu-Chi Chen

Inventor： Jih-Wen Chou ,  Yu-Chi Chen

IPC: H01L21/8242

CPC classification number: H01L27/1087 ,  H01L27/10867 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.

Abstract translation: 提供了动态随机存取存储器（DRAM）。 动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层， 门结构。 第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。 设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。 栅极结构设置在基板上。 栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

公开(公告)号：US20080231636A1

公开(公告)日：2008-09-25

申请号：US11747159

申请日：2007-05-10

Applicant: Cheng Jer Yang ,  Shu Ching Yang ,  Hong Ming Chang ,  Hung Wen Chiou

Inventor： Cheng Jer Yang ,  Shu Ching Yang ,  Hong Ming Chang ,  Hung Wen Chiou

IPC: G06T11/20

CPC classification number: G05B23/0229

Abstract: A dynamic fault detection method comprises the steps of acquiring a data curve from a machine, performing a waveform-recognition process to check if the data curve includes an effective waveform, performing a data-diagnosing process to check if the value of the effective waveform in an effective region falls outside a predetermined range, and generating an alarm signal if the value of the effective waveform in the effective region falls outside the predetermined range. The waveform-recognition process comprises the steps of checking if the data curve includes a first segment, a second segment and a third segment sandwiched between the first segment and the second segment, and checking if the length of the third segment is larger than a predetermined value. The waveform is determined to include the effective waveform if the checking results are true.

Abstract translation: 动态故障检测方法包括以下步骤：从机器获取数据曲线，执行波形识别处理以检查数据曲线是否包括有效波形，执行数据诊断处理以检查有效波形的值是否在 有效区域落在预定范围之外，并且如果有效区域中的有效波形的值落在预定范围之外，则产生报警信号。 波形识别处理包括以下步骤：检查数据曲线是否包括第一段，第二段和夹在第一段与第二段之间的第三段，以及检查第三段的长度是否大于预定的 值。 如果检查结果为真，则波形被确定为包括有效波形。

公开(公告)号：US07419872B2

公开(公告)日：2008-09-02

申请号：US11561957

申请日：2006-11-21

Applicant: Ching Lee ,  Chin Wen Lee ,  Chin Long Hung ,  Zheng Cheng Chen

Inventor： Ching Lee ,  Chin Wen Lee ,  Chin Long Hung ,  Zheng Cheng Chen

IPC: H01L21/8242

CPC classification number: H01L29/66181

Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.

Abstract translation: 制备沟槽电容器结构的方法首先在衬底中形成至少一个沟槽，并且在沟槽的底部形成电容器结构，其中电容器结构包括位于沟槽的下外表面上的掩埋底电极， 覆盖所述底部电极的内表面的第一电介质层和位于所述电介质层的表面上的顶部电极。 随后，在顶部电极上方的第一介电层的表面上形成轴环绝缘层，然后在轴环绝缘层中形成第一导电块。 具有掺杂剂的第二导电块形成在第一导电块上，并且执行热处理工艺以将掺杂剂从第二导电块扩散到半导体衬底的上部以形成掩埋导电区域。

公开(公告)号：US20080199614A1

公开(公告)日：2008-08-21

申请号：US11790432

申请日：2007-04-25

Applicant: Ming-Yen Li ,  Hsiao-Che Wu

Inventor： Ming-Yen Li ,  Hsiao-Che Wu

IPC: C23C16/00

CPC classification number: C23C16/45544 ,  C23C16/4557 ,  C23C16/45572 ,  C23C16/46 ,  C23C16/463

Abstract: A method for improving atomic layer deposition (ALD) performance and an apparatus thereof are disclosed. The apparatus alternates the process temperature of the different ALD steps rapidly, and the process temperature of each step is determined in accordance with the specific precursor and the substrate surface used. In case a higher process temperature is needed, a plurality of heating units of the apparatus increases and keeps the temperature of the deposited substrate to complete surface reaction. When the lower process temperature is needful for the next ALD step, the heating units are turned off to reduce the temperature of the deposited substrate and a gas flow puffed to the heater and the deposited substrate to assist in temperature cooling.

Abstract translation: 公开了一种改善原子层沉积（ALD）性能的方法及其装置。 该装置可以快速地改变不同ALD步骤的工艺温度，并根据具体的前体和所使用的基材表面确定每个步骤的工艺温度。 在需要更高的工艺温度的情况下，该装置的多个加热单元增加并保持沉积的基板的温度以完成表面反应。 当下一个ALD步骤需要较低的工艺温度时，加热单元被关闭以降低沉积的基板的温度，并将气流膨胀到加热器和沉积的基板以辅助温度冷却。

公开(公告)号：US20080157050A1

公开(公告)日：2008-07-03

申请号：US11617977

申请日：2006-12-29

Applicant: Frederick T Chen

Inventor： Frederick T Chen

IPC: H01L29/04 ,  H01L21/306 ,  G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor.

Abstract translation: 一种相变存储器及其制造方法。 相变存储器包括晶体管和相变材料层。 特别地，相变材料层与晶体管的一个电端子直接接触。 特别地，晶体管可以是场效应晶体管或双极结型晶体管。

公开(公告)号：US07394124B2

公开(公告)日：2008-07-01

申请号：US11307424

申请日：2006-02-07

Applicant: Jih-Wen Chou ,  Yu-Chi Chen

Inventor： Jih-Wen Chou ,  Yu-Chi Chen

IPC: H01L29/94

CPC classification number: H01L27/1087 ,  H01L27/10867 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.

Abstract translation: 提供了动态随机存取存储器（DRAM）。 动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层， 门结构。 第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。 设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。 栅极结构设置在基板上。 栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

公开(公告)号：US20080151613A1

公开(公告)日：2008-06-26

申请号：US11959108

申请日：2007-12-18

Applicant: Te-Sheng Chao ,  Ming-Jung Chen ,  Philip H. Yeh ,  Ming-Jinn Tsai

Inventor： Te-Sheng Chao ,  Ming-Jung Chen ,  Philip H. Yeh ,  Ming-Jinn Tsai

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.

Abstract translation: 公开了一种基于非晶相和晶相之间的相变的相变存储器的编程方法。 编程方法包括具有阶跃波形的电流脉冲，其向相变存储器提供第一结晶电流脉冲，并向相变存储器提供第二结晶电流脉冲。 第一结晶电流脉冲具有保持第一保持时间的第一上升沿，第一下降沿和第一峰值电流。 第二结晶电流脉冲具有第二峰值电流。 第二峰值电流遵循第一下降沿并保持第二保持时间。

公开(公告)号：US20080138970A1

公开(公告)日：2008-06-12

申请号：US11670427

申请日：2007-02-02

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/28

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66583

Abstract: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.