公开(公告)号：US20250138428A1

公开(公告)日：2025-05-01

申请号：US19010913

申请日：2025-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei WANG ,  Wei-Han LAI ,  Ching-Yu CHANG

IPC: G03F7/32 ,  G03F7/11 ,  G03F7/30 ,  H01L21/02 ,  H01L21/027

Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.

公开(公告)号：US12288722B2

公开(公告)日：2025-04-29

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US12288703B2

公开(公告)日：2025-04-29

申请号：US18365766

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Sung Hung ,  Chia-Lun Chen ,  Cheng-Hao Kuo

IPC: H01L21/67 ,  G01H17/00 ,  H01L21/66

Abstract: The present disclosure provides a system and method for determining condition of wafers during processing of the wafers. The system and method include detecting vibrations of a wafer transfer robot, generating signals based upon the vibrations, and processing the signals for determining a condition of the wafers held by the wafer transfer robot.

公开(公告)号：US12288021B2

公开(公告)日：2025-04-29

申请号：US18444142

申请日：2024-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Wei Kuo ,  Wen-Shiang Liao

IPC: G06F30/392 ,  G02B27/00 ,  G05B19/18 ,  G06F30/39 ,  G06F30/394 ,  G06F30/398 ,  G02B6/122 ,  G02B6/124

Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.

公开(公告)号：US12286706B2

公开(公告)日：2025-04-29

申请号：US17187410

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi Shen ,  Hsin-Lin Wu ,  Yao-Fong Dai ,  Pei-Yuan Tai ,  Chin-Wei Chen ,  Yin-Tun Chou ,  Yuan-Hsin Chi ,  Sheng-Yuan Lin

IPC: C23C14/56 ,  C23C14/50 ,  C23C16/455 ,  H01L21/687

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

公开(公告)号：US12286306B2

公开(公告)日：2025-04-29

申请号：US17384360

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Hsu ,  Guancyun Li ,  Ching-Jung Chang ,  Chi-Feng Tung ,  Hsiang-Yin Shen

IPC: B65G43/02 ,  B61B3/00 ,  G01B21/22 ,  G01C9/06 ,  G01H1/00 ,  H01L21/677

Abstract: An overhead transport system is provided capable of absorbing abnormal vibration and determining a source of the abnormal vibration. The overhead transport system in accordance with various embodiments of the present disclosure includes a processor, an overhead rail, a plurality of hangers that support the overhead rail, a vibration meter measuring vibration from the overhead rail, and a damper included in each of the hangers. The processor is configured to change a property of the damper in response to a determination that the measured vibration by the vibration meter is indicative of an abnormal vibration.

公开(公告)号：US20250133759A1

公开(公告)日：2025-04-24

申请号：US18420550

申请日：2024-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiu Chiang ,  Pei Ying Lai ,  Cheng-Hao Hou ,  Chi On Chui ,  Shan-Mei Liao ,  Hung-Chi Wu

IPC: H01L29/66 ,  H01L29/78

Abstract: A method forming a source/drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas comprising nitrogen and hydrogen, performing a drive-in process to drive a dipole dopant in the dipole film into the high-k dielectric layer, and depositing a work-function layer on the high-k dielectric layer.

公开(公告)号：US20250133716A1

公开(公告)日：2025-04-24

申请号：US18999095

申请日：2024-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/764 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature. The second dielectric layer and the first dielectric layer have different etch resistance.

公开(公告)号：US20250132191A1

公开(公告)日：2025-04-24

申请号：US18408205

申请日：2024-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ging Lin

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. The first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. The gate isolations are spaced part from the fin isolation regions.

公开(公告)号：US20250132190A1

公开(公告)日：2025-04-24

申请号：US18382273

申请日：2023-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan LIU

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.