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130 条记录 (耗时 0.025 秒)

    Data managment for cache memory
    32.
    发明授权
    Data managment for cache memory 有权

    公开(公告)号：US09798672B1

    公开(公告)日：2017-10-24

    申请号：US15098573

    申请日：2016-04-14

    申请人： APPLIED MICRO CIRCUITS CORPORATION

    发明人： Kjeld Svendsen ,  John Gregory Favor

    IPC分类号： G06F12/08 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0897

    CPC分类号： G06F12/0891 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/45 ,  G06F2212/60

    摘要： Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.

    Operating a FIFO memory
    33.
    发明授权
    Operating a FIFO memory 有权

    公开(公告)号：US09767034B2

    公开(公告)日：2017-09-19

    申请号：US14708787

    申请日：2015-05-11

    申请人： EM MICROELECTRONIC-MARIN SA

    发明人： Jean-Michel Daga ,  Alexandre Deschildre

    IPC分类号： G06F12/08 ,  G06F12/0891 ,  G06F5/06 ,  G06F5/12

    CPC分类号： G06F12/0891 ,  G06F5/06 ,  G06F5/12 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/45

    摘要： The present invention concerns a method of operating a first-in first-out memory (9) arranged to store measurement data samples measured by a plurality of data measurement sensors (1, 3, 5), which can operate at various sampling rates. The oldest measurement data sample in the memory (9) is arranged to be read first before the newer measurement data samples. The method comprises: receiving measurement data samples from at least two data measurement sensors (1, 3, 5); and saving the received measurement data samples in the memory (9). Each of the measurement data samples saved in the memory is associated with a tag which is also saved in the memory (9) and which identifies the data measurement sensor (1, 3, 5) which measured the respective measurement data sample.

    MEDICAL DEVICE USER CACHING
    37.
    发明申请
    MEDICAL DEVICE USER CACHING 审中-公开

    公开(公告)号：US20170140134A1

    公开(公告)日：2017-05-18

    申请号：US14941843

    申请日：2015-11-16

    申请人： Welch Allyn, Inc.

    发明人： Stacie L. Brough ,  Andrew Brayton Nye, III

    IPC分类号： G06F21/31 ,  G06F19/00 ,  A61B5/00 ,  G06F12/08

    CPC分类号： G06F21/31 ,  A61B5/0002 ,  A61B5/002 ,  A61B5/02055 ,  A61B2560/0266 ,  A61B2560/0437 ,  G06F12/0875 ,  G06F19/3418 ,  G06F2212/1052 ,  G06F2212/45

    摘要： An example medical device includes a physiological measurement device, a device management engine, a user caching engine, and a login engine. The device management engine is configured to receive data captured by the physiological measurement device. The user caching engine is configured to store cache records associated with users in a user cache. The login engine is configured to receive a user identifier associated with a user and determine whether the user identifier is associated with a cache record stored in the user cache. When determined that the user identifier is associated with a cache record stored in the user cache, the login engine is configured to log the user in. When not determined that the user identifier is associated with an unexpired cache record stored in the user cache, the login engine is configured to prompt the user for a credential.

    Memory circuit and cache circuit configuration
    40.
    发明授权
    Memory circuit and cache circuit configuration 有权
    存储电路和缓存电路配置

    公开(公告)号：US09431064B2

    公开(公告)日：2016-08-30

    申请号：US13667924

    申请日：2012-11-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hsien-Hsin Sean Lee ,  William Wu Shen ,  Yun-Han Lee

    IPC分类号： G11C5/02 ,  G11C5/04

    CPC分类号： G06F12/0804 ,  G06F12/0891 ,  G06F2212/1008 ,  G06F2212/1032 ,  G06F2212/45 ,  G06F2212/608 ,  G11C5/025 ,  G11C5/04 ,  G11C7/22

    摘要： A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.

    摘要翻译： 高速缓冲存储器管芯包括衬底，衬底上的预定数量的存储器单元组，高速缓冲存储器管芯的第一表面上的第一组输入/输出端子和第二组输入/输出端子 缓冲存储器表面死亡。 第一组输入/输出端子连接到高速缓冲存储器管芯外部的主存储器电路。 第二组输入/输出端子的一部分与第一组输入/输出端子兼容。