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72 条记录 (耗时 0.014 秒)

    Sense latch
    31.
    发明授权
    Sense latch 失效
    感应锁

    公开(公告)号：US4279023A

    公开(公告)日：1981-07-14

    申请号：US105050

    申请日：1979-12-19

    申请人： Russell J. Houghton

    发明人： Russell J. Houghton

    IPC分类号： G11C11/416 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4067 ,  G11C11/409 ,  G11C11/411 ,  G11C11/40

    CPC分类号： G11C11/411 ,  G11C11/403 ,  G11C11/4067

    摘要： This describes a sense latch for a bipolar dynamic array in which each cell is comprised of a capacitor and a pnp-npn transistor. Cell information is stored in the capacitor. The capacitor may be either a discreet capacitor or may be formed as part of the base node of the pnp transistor. The sense latch of the invention comprises a pair of cross coupled transistors coupled between a pair of capacitively loaded bit lines of the array with one of the bit lines being coupled to a data cell and the other being coupled to a reference cell. Means for precharging the bit lines to a fixed voltage level and means for reading the cell to charge one of the bit lines to a level greater than the precharge level and apply a differential signal to the latch are also provided so that during the reading cycle one of the transistors in the latch becomes turned on so that the voltage levels of both bit lines are determined by the characteristics of the turned on transistor only. The voltage on one line is determined by the forward base-emitter characteristics of the turned on transistor and the voltage on the other line is determined by the saturated collector-emitter characteristics of the same turned on transistor.

    摘要翻译： 这描述了双极性动态阵列的检测锁存器，其中每个单元由电容器和pnp-npn晶体管组成。 单元信息存储在电容器中。 电容器可以是离散电容器，也可以形成为pnp晶体管的基极节点的一部分。 本发明的检测锁存器包括一对交叉耦合的晶体管，其耦合在该阵列的一对电容负载的位线之间，其中一个位线耦合到数据单元，另一个耦合到参考单元。 用于将位线预充电到固定电压电平的装置，以及用于读取单元以将位线中的一个充电至大于预充电电平的电平并向差分信号施加差分信号的装置，使得在读周期期间 锁存器中的晶体管变为导通，使得两个位线的电压电平仅由导通晶体管的特性决定。 一条线上的电压由导通晶体管的正向基极 - 发射极特性决定，另一条线上的电压由相同的导通晶体管的饱和集电极 - 发射极特性决定。

    Two-terminal npn-pnp transistor memory cell
    32.
    发明授权
    Two-terminal npn-pnp transistor memory cell 失效
    两端NPN-PNP晶体管存储单元

    公开(公告)号：US3715732A

    公开(公告)日：1973-02-06

    申请号：US3715732D

    申请日：1971-12-09

    申请人： BELL TELEPHONE LABOR INC

    发明人： LYNES D

    IPC分类号： G11C11/41 ,  G11C11/403 ,  G11C11/405 ,  G11C11/411 ,  H01L21/8229 ,  H01L27/102 ,  G11C11/40 ,  G11C11/24

    CPC分类号： G11C11/411 ,  G11C11/403

    摘要： A semiconductor memory array contains memory cells each of which contains an NPN transistor and a PNP transistor. The collector and base of the NPN transistor are respectively coupled to the base and collector of the PNP transistor. Bit information is written into the cell by causing or inhibiting conduction in the PNP transistor in order to set the potential of the base of the NPN transistor to one of two values which represent, respectively, a ''''1'''' and a ''''0.'''' A positive polarity voltage pulse applied to the collector of the NPN transistor causes information previously stored in the cell to be read out.

    Storage circuit
    33.
    发明授权
    Storage circuit 失效
    存储电路

    公开(公告)号：US3599184A

    公开(公告)日：1971-08-10

    申请号：US3599184D

    申请日：1969-07-10

    申请人： RCA CORP

    发明人： BEINART JEFFRY HUGH ,  HAMPEL DANIEL

    IPC分类号： G11C11/411 ,  G11C19/28 ,  H03K3/037 ,  G11C11/40 ,  G11C19/00

    CPC分类号： H03K3/037 ,  G11C11/411 ,  G11C19/28

    摘要： A plurality of two-input logic gates such as OR gates supplying their outputs to a three-input logic gate such as an AND gate and including a feedback connection from the three-input gate to all but one of the two-input gates. A control signal is applied to the two-input gate not receiving feedback and the complement of this control signal is applied to one of the other two-input gates. An information signal is applied to the two-input gate not receiving feedback and to a two-input gate not receiving the complement of the control signal.

    COMPLEMENTARY BIPOLAR SRAM
    40.
    发明申请
    COMPLEMENTARY BIPOLAR SRAM 有权

    公开(公告)号：US20170236824A1

    公开(公告)日：2017-08-17

    申请号：US15581646

    申请日：2017-04-28

    申请人： International Business Machines Corporation

    发明人： Tak H. Ning

    IPC分类号： H01L27/102 ,  H01L21/8229 ,  H01L21/8228 ,  G11C11/416 ,  G11C11/411

    CPC分类号： G11C11/416 ,  G11C11/411 ,  G11C11/4116 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/1025 ,  H01L27/11

    摘要： A method of forming a complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.