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公开(公告)号：US11836461B2
公开(公告)日：2023-12-05
申请号：US17425055
申请日：2020-01-17
发明人： Hiroshi Yoshida
摘要： An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.
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公开(公告)号：US11836460B2
公开(公告)日：2023-12-05
申请号：US17171174
申请日：2021-02-09
发明人： Theo Alan Drane
IPC分类号： G06F7/535 , G06F30/327 , G06F30/34 , G06F7/523 , G06F7/38
CPC分类号： G06F7/523 , G06F7/38 , G06F7/535 , G06F30/327 , G06F30/34 , G06F2207/5356
摘要： A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.
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公开(公告)号：US11809837B2
公开(公告)日：2023-11-07
申请号：US17012916
申请日：2020-09-04
发明人： Ankur Agrawal , Martin Cochet , Jonathan E. Proesel , Sergey Rylov , Bodhisatwa Sadhu , Hyunkyu Ouh
摘要： A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.
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34.发明公开公开(公告)号：US20230315567A1
公开(公告)日：2023-10-05
申请号：US18332647
申请日：2023-06-09
申请人： SK hynix Inc.
发明人： Jeong Jun LEE , Choung Ki SONG
CPC分类号： G06F11/1048 , G06F7/50 , G06F7/523 , G06F7/5443
摘要： There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.
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35.发明授权公开(公告)号：US11775256B2
公开(公告)日：2023-10-03
申请号：US18096559
申请日：2023-01-12
CPC分类号： G06F7/4876 , G06F7/523 , G06F9/3001 , G06F9/30021
摘要： An N×N multiplier may include a N/2×N first multiplier, a N/2×N/2 second multiplier, and a N/2×N/2 third multiplier. The N×N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2N/2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2N/2 and the other operand is equal to or greater than 2N/2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2N/2, the first, second and third multipliers are used to multiply the operands.
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公开(公告)号：US20230289142A1
公开(公告)日：2023-09-14
申请号：US18111008
申请日：2023-02-17
申请人： Lightmatter, Inc.
发明人： Nicholas C. Harris , Darius Bunandar , Michael Gould , Carl Ramey , Shashank Gupta , Carlos Dorta-Quinones
摘要： Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.
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公开(公告)号：US11748061B2
公开(公告)日：2023-09-05
申请号：US17071875
申请日：2020-10-15
申请人： Mark Ashley Mathews
发明人： Mark Ashley Mathews
摘要： A mass multiplier implemented as an integrated circuit has a port receiving a stream of discrete values and circuitry multiplying each value as received by a plurality of weight values simultaneously. An output channel provides products of the mass multiplier as produced. The mass multiplier is applied to neural network nodes.
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公开(公告)号：US11740869B2
公开(公告)日：2023-08-29
申请号：US17242353
申请日：2021-04-28
发明人： Rajat Rao
CPC分类号： G06F7/523 , G06F7/50 , G06F7/57 , H04L9/3066
摘要： Embodiments are directed to selecting a multiplication operation to be scheduled in a first stage of an execution schedule, the multiplication operation meeting a first condition of having no dependency. An addition/subtraction operation is selected to be scheduled in the first stage of the execution schedule responsive to meeting the first condition. A process is performed which includes selecting another multiplication operation to be scheduled in a next stage of the execution schedule responsive to meeting the first condition or a second condition, the second condition including having a dependency that is fulfilled by a previous stage. The process includes selecting another addition/subtraction operation to be scheduled in the next stage of the execution schedule responsive to meeting the first or second condition, and repeating the process until each operation has been scheduled in the execution schedule, where the execution schedule is configured for execution by an arithmetic logic unit.
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公开(公告)号：US20230253032A1
公开(公告)日：2023-08-10
申请号：US18303194
申请日：2023-04-19
发明人： Yu-Hsuan Lin , Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
IPC分类号： G11C11/4093 , G11C11/4091 , G06F7/523 , G11C11/408 , G06F7/501 , G11C11/4094
CPC分类号： G11C11/4093 , G11C11/4091 , G06F7/523 , G11C11/4085 , G06F7/501 , G11C11/4094
摘要： An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.
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公开(公告)号：US20230221883A1
公开(公告)日：2023-07-13
申请号：US18118634
申请日：2023-03-07
申请人： SK hynix Inc.
发明人： Se Ho KIM , Choung Ki SONG
CPC分类号： G06F3/0655 , G06F3/0604 , G06F7/50 , G06F3/0673 , G06F7/523
摘要： A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.
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