公开(公告)号：US08917123B2

公开(公告)日：2014-12-23

申请号：US13853247

申请日：2013-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil Bahl ,  Shray Khullar

IPC: H03L7/00 ,  H03K3/012

CPC classification number: H03K3/012 ,  G01R31/318575

Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。

公开(公告)号：US20140361915A1

公开(公告)日：2014-12-11

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane LE TUAL ,  Pratap Narayan SINGH

IPC: H03M1/08 ,  H03K3/013

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CPGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CPGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US20140300386A1

公开(公告)日：2014-10-09

申请号：US14231026

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin JAIN ,  Nitin GUPTA

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters.

Abstract translation: 电平移位电路包括第一反相器，其包括具有相反导电类型的一对晶体管，第一反相器适于接收第一电压域中的输入信号，并且还包括由第二电压域中的电压驱动的至少一个附加晶体管。 第二反相器与第一反相器串联耦合并且可操作以在第二电压域中产生输出信号。 第二反相器包括一对相反导电类型的晶体管，并且还包括由第一电压域中的电压驱动的至少一个附加晶体管。 附加晶体管可操作以近似均衡由第一和第二逆变器产生的输出信号的下降时间。

公开(公告)号：US20140292385A1

公开(公告)日：2014-10-02

申请号：US13853247

申请日：2013-03-29

Applicant: STMicroelectronics International N.V.

Inventor： SWAPNIL BAHL ,  Shray Khullar

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G01R31/318575

Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。

公开(公告)号：US20140269137A1

公开(公告)日：2014-09-18

申请号：US14289072

申请日：2014-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Vivek ASTHANA

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract translation: 存储器体包括存储器单元和用于确定存储体的工作电压的附加单元。 附加单元具有小于存储体中其它存储单元的对应操作裕度的操作裕度。

公开(公告)号：US08782480B2

公开(公告)日：2014-07-15

申请号：US14019329

申请日：2013-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Parul Bansal

IPC: G06F11/00

CPC classification number: G01R31/3177 ,  G06F11/3656

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract translation: 片上功能调试器包括一个或多个功能块，每个功能块提供一个或多个功能输出。 分层选择树由具有选择器之一的输出的一个或多个选择器形成为最终输出，以及耦合到功能块的功能输出或另一个选择器的输出的单独选择器输入。 选择信号，其耦合到每个选择器的选择输入以使得其输出中的所选择的一个。 耦合到最终输出的输出节点。 还提供了一种提供片上功能调试的方法。 选择来自一个或多个可用功能输出的期望的功能输出，然后所选择的功能输出耦合到输出节点。

公开(公告)号：US20140161359A1

公开(公告)日：2014-06-12

申请号：US14068437

申请日：2013-10-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L

Inventor： Luca MAGRI ,  Beatrice ROSSI ,  Subarna TRIPATHI ,  Pasqualina FRAGNETO ,  Emiliano Mario PICCINELLI

IPC: G06K9/46

CPC classification number: G06K9/4604 ,  G06T7/13 ,  G06T2207/20061

Abstract: An embodiment is a computer-implemented method for detecting a straight line in a digital image comprising a plurality of pixels comprising the steps: detecting an edge in the digital image, generating a first straight line which passes through a first pixel of the detected edge, generating a second straight line which passes through a second pixel of the detected edge, which is different from the first pixel, determining at least two intersections with a boundary of the digital image for each generated straight line, determining a set of two parameter values for each generated straight line based on the respective determined at least two intersections, wherein the set of two parameter values uniquely determines the respective generated straight line, and detecting the straight line in the digital image based on the determined sets of two parameter values.

Abstract translation: 一个实施例是用于检测包括多个像素的数字图像中的直线的计算机实现的方法，包括以下步骤：检测数字图像中的边缘，生成穿过检测到的边缘的第一像素的第一直线， 产生穿过所检测的边缘的不同于第一像素的第二像素的第二直线，为每个生成的直线确定与数字图像的边界的至少两个交点，确定一组两个参数值，以供 每个生成的直线基于相应确定的至少两个交点，其中所述两个参数值的集合唯一地确定相应生成的直线，并且基于所确定的两个参数值的集合来检测数字图像中的直线。

公开(公告)号：US08724374B1

公开(公告)日：2014-05-13

申请号：US13655160

申请日：2012-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C5/14 ,  G11C11/41 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。

公开(公告)号：US20140070843A1

公开(公告)日：2014-03-13

申请号：US14075272

申请日：2013-11-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Mayank Kumar SINGH ,  Daljeet KUMAR ,  Hiten ADVANI

IPC: H03K19/003

CPC classification number: H03K19/00346 ,  H04L25/0278 ,  H04L25/0298

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract translation: 实施例包括具有校准器的阻抗校准电路，该校准器被配置为比较外部节点处的电压电平和阻抗校准电路的内部节点，并且基于该比较来生成输出。 校准器还包括耦合在外部节点和比较器的第一输入端之间以及内部节点和比较器的第二输入端之间的相应滤波器。 滤波器被配置为从内部节点处的可编程电阻器耦合到的芯片地线将对称噪声注入到比较器中。

公开(公告)号：US20140055438A1

公开(公告)日：2014-02-27

申请号：US14069026

申请日：2013-10-31

Applicant: STMicroelectronics International N.V.

Inventor： Surinder Pal Singh ,  Kaushik Saha ,  Sumit Johar

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G06T1/00

Abstract: An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic.

Abstract translation: 图像处理装置包括用于接收与图像处理装置相关的功率特性的指示符的输入和基于功率特性的指标来处理图像的图像处理器。