公开(公告)号：US07226764B1

公开(公告)日：2007-06-05

申请号：US09709020

申请日：2000-11-08

Applicant: Christoph Benning ,  Sherrie Lea Sanda ,  Bin Yu

Inventor： Christoph Benning ,  Sherrie Lea Sanda ,  Bin Yu

IPC: C12P7/00 ,  C12N9/00 ,  C12N9/10 ,  C12N1/20 ,  C12N15/00 ,  C12Q21/04 ,  C07H21/04 ,  C12Q1/00 ,  C12Q1/68 ,  C12Q1/48

CPC classification number: C12P19/42

Abstract: The present invention is directed to compositions and methods related to the synthesis and modification of uridine-5′-diphospho-sulfoquinovose (UDP-SQ). In particular, the methods of the present invention comprise the utilization of recombinant enzymes from Arabidopsis thaliana, UDP-glucose, and a sulfur donor to synthesize UDP-SQ, and the subsequent modification of UDP-SQ to form compounds including, but not limited to, 6-sulfo-α-D-quinovosyl diaclyglycerol (SQDG) and alkyl sulfoquinovoside. The compositions and methods of the invention provide a more simple, rapid means of synthesizing UDP-SQ, and the subsequent modification of UDP-SQ to compounds including, but not limited to, SQDG.

Abstract translation: 本发明涉及与尿苷-5'-二磷酸 - 磺基奎诺糖（UDP-SQ）的合成和修饰相关的组合物和方法。 特别地，本发明的方法包括利用来自拟南芥，UDP-葡萄糖和硫供体的重组酶合成UDP-SQ，以及后续的UDP-SQ修饰以形成化合物，包括但不限于 ，6-磺基-α-D-喹喔啉基二甘油（SQDG）和烷基磺基喹诺酮。 本发明的组合物和方法提供了一种更简单，快速的方法来合成UDP-SQ，以及随后将UDP-SQ修饰为化合物，包括但不限于SQDG。

公开(公告)号：US07186599B2

公开(公告)日：2007-03-06

申请号：US10754540

申请日：2004-01-12

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。

公开(公告)号：US07148526B1

公开(公告)日：2006-12-12

申请号：US10348758

申请日：2003-01-23

Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

Abstract translation: 双栅极锗金属氧化物半导体场效应晶体管（MOSFET）包括锗翅片，邻近锗翅片的第一侧形成的第一栅极和与第一侧相对的锗翅片第二侧附近形成的第二栅极 。 三栅极MOSFET包括锗翅片，与锗翅片的第一侧相邻形成的第一栅极，与第一侧相对的锗翅片的第二侧附近形成的第二栅极和形成在锗翅片顶部上的顶栅极 。 全栅极MOSFET包括锗翅片，邻近锗翅片的第一侧形成的第一侧壁栅极结构，邻近锗翅片的第二侧形成的第二侧壁栅极结构，以及形成在锗翅片上和周围的附近的栅极结构 锗鳍

公开(公告)号：US07091068B1

公开(公告)日：2006-08-15

申请号：US10310776

申请日：2002-12-06

Applicant: Shibly S. Ahmed ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在栅极结构上沉积栅极材料。 该方法还可以包括在栅极材料上形成牺牲材料并平坦化牺牲材料。 可以在平坦化的牺牲材料上沉积抗反射涂层。 然后可以通过蚀刻栅极材料形成栅极结构。

公开(公告)号：US07064022B1

公开(公告)日：2006-06-20

申请号：US10728844

申请日：2003-12-08

Applicant: Wiley Eugene Hill ,  Ming-Ren Lin ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/7854 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/66795

Abstract: A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.

Abstract translation: 一种方法从包括通过绝缘层与第二源极区域，第二漏极区域和第二鳍状结构分离的第一源极区域，第一漏极区域和第一鳍状物结构的器件形成半导体器件。 该方法可以包括在器件上形成电介质层并去除介电层的部分以产生被覆盖部分和裸露部分。 该方法还可以包括在覆盖部分和裸露部分上沉积栅极材料，用第一材料掺杂第一鳍片结构，第一源极区域和第一漏极区域，并掺杂第二鳍片结构，第二源极区域， 和具有第二材料的第二漏区。 该方法还可以包括在至少一个被覆部分上去除栅极材料的一部分以形成半导体器件。

公开(公告)号：US07034361B1

公开(公告)日：2006-04-25

申请号：US10653234

申请日：2003-09-03

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795

Abstract: A semiconductor device includes a fin, a source region formed adjacent the fin and having a height greater than that of the fin, and a drain region formed adjacent the a second side of the fin and having a height greater than that of the fin. A metal gate region is formed at a top surface and at least one side surface of the fin. A width of the source and drain region may be greater than that of the fin. The semiconductor device may exhibit a reduced series resistance and an improved transistor drive current.

Abstract translation: 半导体器件包括鳍状物，邻近翅片形成的源极区域，其高度大于鳍状物的高度;以及漏极区域，其形成在翅片的第二侧附近并且具有高于翅片的高度。 金属栅极区域形成在翅片的顶表面和至少一个侧表面处。 源极和漏极区域的宽度可以大于鳍片的宽度。 半导体器件可以呈现减小的串联电阻和改进的晶体管驱动电流。

公开(公告)号：US07029959B1

公开(公告)日：2006-04-18

申请号：US10429737

申请日：2003-05-06

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murhty ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murhty ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the organic anti-reflective coating. The organic anti-reflective coating around the gate mask may be removed, and the gate material around the gate mask may be removed to define a gate.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在栅极结构上沉积栅极材料。 该方法还可以包括在栅极材料上沉积有机抗反射涂层并在有机抗反射涂层上形成栅极掩模。 可以去除栅极掩模周围的有机抗反射涂层，并且可以去除栅极掩模周围的栅极材料以限定栅极。

公开(公告)号：US07029958B2

公开(公告)日：2006-04-18

申请号：US10699887

申请日：2003-11-04

Applicant: Cyrus E. Tabery ,  Shibly S. Ahmed ,  Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Cyrus E. Tabery ,  Shibly S. Ahmed ,  Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7842

Abstract: A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

Abstract translation: 一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在衬底上构图翅片区域，源极区域和漏极区域，在翅片区域中形成鳍片，并在鳍片区域中形成掩模 。 该方法还包括蚀刻掩模以暴露MOSFET的沟道区域，蚀刻鳍以在沟道区域中减薄翅片的宽度，在鳍上方形成栅极，以及形成与栅极，源区和 漏极区域。

公开(公告)号：US06979635B1

公开(公告)日：2005-12-27

申请号：US10759171

申请日：2004-01-20

Applicant: Akif Sultan ,  Qi Xiang ,  Bin Yu

Inventor： Akif Sultan ,  Qi Xiang ,  Bin Yu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract translation: 通过图案化多晶硅栅极前体，通过选择性地氧化其上表面和侧表面，然后去除氧化表面而减小其宽度和高度来形成超窄和多晶硅栅电极。 实施例包括用其下面的氧化物层图案化多晶硅栅极前体，离子注入以形成深源极/漏极区域，在多晶硅栅极前体的每一侧的衬底表面上形成氮化物层，热氧化多晶硅的上表面和侧表面 从而消耗硅，然后去除氧化的上表面和侧表面，留下具有减小的宽度和降低的高度的多晶硅栅电极。 随后的处理包括形成浅源极/漏极延伸部分，在多晶硅栅电极上形成电介质侧壁间隔物，然后在多晶硅栅极电极的上表面上以及在源极/漏极区域上形成金属硅化物层。

公开(公告)号：US20050153492A1

公开(公告)日：2005-07-14

申请号：US10754559

申请日：2004-01-12

Applicant: Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/338

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a dummy gate over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the dummy gate to form a trench in the dielectric layer and forming a metal gate in the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括形成鳍片并形成与鳍片的第一端相邻的源极区域和与鳍片的第二端部相邻的漏极区域。 该方法还包括在鳍上方形成虚拟栅极，并在虚拟栅极周围形成电介质层。 该方法还包括去除伪栅极以在电介质层中形成沟槽并在沟槽中形成金属栅极。