公开(公告)号：US11741232B2

公开(公告)日：2023-08-29

申请号：US17163599

申请日：2021-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

CPC classification number: G06F21/572 ,  G06F8/65 ,  G06F9/445 ,  G06F2221/033

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US11740985B2

公开(公告)日：2023-08-29

申请号：US17241079

申请日：2021-04-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ran Koren ,  Shay Aisman ,  Itamar Rabenstein ,  Amir Ancel

IPC: G06F11/273 ,  G06F13/20 ,  G06F11/22 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/273 ,  G06F11/2268 ,  G06F11/3072 ,  G06F11/3075 ,  G06F11/3476 ,  G06F11/3485 ,  G06F13/20 ,  G06F11/3013 ,  G06F11/348

Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

公开(公告)号：US20230269684A1

公开(公告)日：2023-08-24

申请号：US17675548

申请日：2022-02-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Timothy James Martin

IPC: H04W56/00

CPC classification number: H04W56/0045

Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.

公开(公告)号：US20230269077A1

公开(公告)日：2023-08-24

申请号：US17683972

申请日：2022-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dimitrios Syrivelis ,  Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Elad Mentovich

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0825 ,  H04L9/0838 ,  H04L9/0852 ,  H04L9/3236

Abstract: Systems, data processing systems, and methods, among other things, are disclosed. An illustrative system includes an encryption orchestrator that analyzes a packet, obtains a tenant identifier (ID) from the packet, determines whether a tenant associated with the tenant ID currently has sufficient encryption credit available, and enables an encryption resource to process the packet using an encryption key associated with the tenant ID in response to determining that the tenant associated with the tenant ID currently has sufficient encryption credit available.

公开(公告)号：US20230269003A1

公开(公告)日：2023-08-24

申请号：US17675669

申请日：2022-02-18

Applicant: Mellanox Technologies, Ltd.

Inventor： Juan Jose Vegas Olmos ,  Elad Mentovich ,  Liran Liss ,  Yonathan Piasetzky

IPC: H04B10/70 ,  H04B10/60 ,  G06N10/40

CPC classification number: H04B10/70 ,  H04B10/60 ,  G06N10/40

Abstract: Embodiments are disclosed for facilitating quantum computing over classical and quantum communication channels. An example system includes a network interface card (NIC) apparatus. The NIC apparatus includes an optical receiver, an embedded processor, and a network switch. The optical receiver is configured to receive qubit data via a first communication channel associated with quantum communication. The embedded processor is configured to convert the qubit data into binary bit data. The network switch is configured to output the binary bit data via a second communication channel associated with classical network communication.

公开(公告)号：US11728623B2

公开(公告)日：2023-08-15

申请号：US17247401

申请日：2020-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuri Berk ,  Vladimir Iakovlev ,  Tamir Sharkaz ,  Elad Mentovich

IPC: H01S5/30 ,  H01S5/183 ,  H01S5/227 ,  H01S5/34 ,  H01S5/42

CPC classification number: H01S5/18347 ,  H01S5/18311 ,  H01S5/18377 ,  H01S5/2275 ,  H01S5/3095 ,  H01S5/3401 ,  H01S5/423

Abstract: A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a mesa structure disposed on a substrate. The mesa structure defines an emission axis of the VCSEL. The mesa structure includes a first reflector, a second reflector, and a cascaded active region structure disposed between the first reflector and the second reflector. The cascaded active region structure includes a plurality of cascaded active region layers disposed along the emission axis, where each of the cascade active region layers includes an active region having multi-quantum well and/or dots layers (MQLs), a tunnel junction aligned with the emission axis, and an oxide confinement layer. The oxide confinement layer is disposed between the tunnel junction and MQLs, and has an electrical current aperture defined therein. The mesa structure defines an optical window through which the VCSEL is configured to emit light.

公开(公告)号：US11726279B2

公开(公告)日：2023-08-15

申请号：US17717623

申请日：2022-04-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Ilya Margolin ,  Rony Setter ,  Andrey Ger ,  Yaniv Kazav ,  Tarek Hathoot

IPC: H04B10/00 ,  G02B6/42 ,  H04B10/40

CPC classification number: G02B6/4261 ,  G02B6/4284 ,  H04B10/40

Abstract: Apparatuses, systems, and methods are described that provide improved networking communication systems and associated adapters. An example networking communication adapter includes an adapter housing defining a first end and a second end opposite the first end. The first end is configured to engage an Octal Small Form Factor Pluggable (OSFP) connector, and the second end is configured to receive a Quad Small Form Factor Pluggable Double Density (QSFP-DD) transceiver therein. The networking communication adapter further includes an inner connector positioned within the adapter housing. In an operational configuration in which the first end engages the OSFP connector and the second end receives the QSFP-DD transceiver, the inner connector operably connects the QSFP-DD transceiver with the OSFP connector such that signals may pass therebetween.

公开(公告)号：US20230239068A1

公开(公告)日：2023-07-27

申请号：US17665600

申请日：2022-02-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ioannis (Giannis) Patronas ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04J14/08 ,  H04J14/02

CPC classification number: H04J14/08 ,  H04J14/0212 ,  H04J14/0267

Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.

公开(公告)号：US20230238358A1

公开(公告)日：2023-07-27

申请号：US17584450

申请日：2022-01-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Ido Bourstein

IPC: H01L25/065 ,  H01L23/00 ,  G03F1/20

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/06 ,  H01L24/80 ,  G03F1/20 ,  H01L2224/08145 ,  H01L2224/06177 ,  H01L2224/80895

Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

公开(公告)号：US20230236624A1

公开(公告)日：2023-07-27

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  H04J3/0697 ,  H04J3/0682 ,  H04J3/0661 ,  H04J3/0679 ,  G06F1/12

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.