公开(公告)号：US5622796A

公开(公告)日：1997-04-22

申请号：US363231

申请日：1994-12-22

Applicant: Paolo Canestrari ,  Samuele Carrera ,  Giovanni Rivera

Inventor： Paolo Canestrari ,  Samuele Carrera ,  Giovanni Rivera

IPC: G01B21/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/66 ,  G03F9/00

CPC classification number: G03F7/70633 ,  G03F7/0035

Abstract: Process for producing metrological structures particularly for direct measurement of errors introduced by alignment systems, whose peculiarity consists in performing, on a same substrate, metrological alignment markings and processed alignment markings according to arrays of preset numerical size.

Abstract translation: 用于生产计量结构的方法，特别是用于直接测量由对准系统引入的误差，其特性包括根据预设数值大小的阵列在同一基板上执行计量校准标记和处理的对准标记。

公开(公告)号：US5621474A

公开(公告)日：1997-04-15

申请号：US345512

申请日：1994-11-28

Applicant: Massimo Mancuso ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

Inventor： Massimo Mancuso ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

IPC: G06F9/44 ,  G06N7/02 ,  G06T5/00 ,  H03H17/00 ,  H04N5/21 ,  H04N5/93 ,  H04N5/213

CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T2207/10016 ,  H03H2222/02

Abstract: A filter acting on digital image signals for apparatus of the video type includes at least first and second processing units adapted to elect an image edge, each processing unit includes an inferential circuit operating on fuzzy logic, which has first and second input terminals and an output terminal, and first and second comparison elements each having first and second input terminals and an output terminal, the input terminals being intended for receiving discrete digital signals of an image. The output terminals of the first and second comparison elements in the first processing unit are respectively connected to the first and second input terminals of the inferential circuit included in the first processing unit, and the output terminals of the first and second comparison elements in the second processing unit are respectively connected to the first and second input terminals of the inferential circuit included in the second processing unit.

Abstract translation: 作为视频类型的装置的数字图像信号的滤波器至少包括适于选择图像边缘的第一和第二处理单元，每个处理单元包括在模糊逻辑上工作的推理电路，该模糊逻辑具有第一和第二输入端子以及输出 端子以及分别具有第一和第二输入端子和输出端子的第一和第二比较元件，输入端子用于接收图像的离散数字信号。 第一处理单元中的第一和第二比较元件的输出端子分别连接到包括在第一处理单元中的推理电路的第一和第二输入端子，第二处理单元中的第一和第二比较元件的输出端子 处理单元分别连接到包括在第二处理单元中的推理电路的第一和第二输入端。

公开(公告)号：US5621358A

公开(公告)日：1997-04-15

申请号：US454924

申请日：1995-05-31

Applicant: Valerio Pisati ,  Roberto Alini ,  Rinaldo Castello ,  Gianfranco Vai

Inventor： Valerio Pisati ,  Roberto Alini ,  Rinaldo Castello ,  Gianfranco Vai

IPC: H03F3/343 ,  H03F3/45 ,  H03G1/00 ,  H03H11/24

CPC classification number: H03F3/45883 ,  H03F3/45286 ,  H03F3/45807 ,  H03G1/0023 ,  H03F2203/45648

Abstract: A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Abstract translation: 包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3）的受控增益跨导体（20），连接到 跨导级和连接在所述输出端子（O1，O2）和有源负载（4）之间的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出，以提供调整装置的DC增益所需的预定电压值（Vc）。

公开(公告)号：US5621353A

公开(公告)日：1997-04-15

申请号：US550850

申请日：1995-10-31

Applicant: Edoardo Botti ,  Tiziana Mandrini

Inventor： Edoardo Botti ,  Tiziana Mandrini

IPC: H03F3/68 ,  H03F3/30 ,  H03F3/45 ,  H03F3/50 ,  H03F3/72 ,  H03F1/14

CPC classification number: H03F3/72 ,  H03F3/3023 ,  H03F3/45192

Abstract: A circuit assembly for an operational amplifier has an input stage with first and second input terminals and an output terminal. An output stage has a first input terminal coupled to the output terminal of the input stage, a second input terminal, and an output terminal. A feedback circuit is coupled between the output terminal of the output stage and the second input terminal of the input stage. An interconnection circuit is coupled to the first and second input terminals and the output terminal of the output stage and to a reference voltage source. The interconnection circuit has first, second, and third modes, such that the second input terminal of the output stage is coupled to the reference voltage source when the interconnection circuit is in the first mode. The first input terminal of the output stage is coupled to the reference voltage source when the interconnection circuit is in the second mode, and the first input terminal of the output stage is coupled to the output terminal of the output stage and the second input terminal of the output stage is coupled to the reference voltage source when the interconnection circuit is in the third mode.

Abstract translation: 用于运算放大器的电路组件具有具有第一和第二输入端子和输出端子的输入级。 输出级具有耦合到输入级的输出端的第一输入端，第二输入端和输出端。 反馈电路耦合在输出级的输出端和输入级的第二输入端之间。 互连电路耦合到输出级的第一和第二输入端子和输出端子以及参考电压源。 互连电路具有第一，第二和第三模式，使得当互连电路处于第一模式时，输出级的第二输入端耦合到参考电压源。 当互连电路处于第二模式时，输出级的第一输入端耦合到参考电压源，输出级的第一输入端耦合到输出级的输出端和第二输入端 当互连电路处于第三模式时，输出级耦合到参考电压源。

公开(公告)号：US5619271A

公开(公告)日：1997-04-08

申请号：US427082

申请日：1995-04-21

Applicant: Massimo Mancuso ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

Inventor： Massimo Mancuso ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

IPC: H04N5/92 ,  H04N5/44 ,  H04N9/80 ,  H04N11/20 ,  H04N7/01

CPC classification number: H04N7/012 ,  H04N7/0132

Abstract: A television signal scanning conversion device of the type comprising at least one filtering block having a plurality of digital inputs which receive through an interface components of an interlaced television signal comprises also at lease one calculation block connected to the signal inputs and operating with fuzzy logic. The calculation block is capable of executing a switch between at least two different interpolation procedures, to wit interfield and intrafield.

Abstract translation: 一种电视信号扫描转换装置，其类型包括至少一个具有多个数字输入的滤波块，该多个数字输入通过接口的隔行扫描电视信号的分量接收，还包括至少一个计算块，其连接到信号输入并用模糊逻辑运行。 计算块能够在至少两个不同的插值程序之间执行切换，即在场间和场内。

公开(公告)号：US5617356A

公开(公告)日：1997-04-01

申请号：US395361

申请日：1995-02-21

Applicant: Carla Golla ,  Silvia Padoan ,  Marco Olivo

Inventor： Carla Golla ,  Silvia Padoan ,  Marco Olivo

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16 ,  G11C16/02

CPC classification number: G11C16/16 ,  G11C16/14

Abstract: A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.

Abstract translation: 一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关， 所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。 还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。 该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。

公开(公告)号：US5612913A

公开(公告)日：1997-03-18

申请号：US533631

申请日：1995-09-25

Applicant: Paolo Cappelletti ,  Giulio Casagrande

Inventor： Paolo Cappelletti ,  Giulio Casagrande

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C16/16

Abstract: A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLASH process is composed by a matrix of FLASH cells organized in n bytes, each of m bits, addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistor. EEPROM functionality is obtained without any modification of the standard FLASH fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.

Abstract translation: 具有可以以完全兼容的方式与标准FLASH处理集成的EEPROM类型功能的字节可擦除存储器由以n字节组织的FLASH单元矩阵组成，每个m位可通过多个字线和位线寻址。 EEPROM型存储器具有由n个字节选择晶体管组成的辅助选择结构，多个单独可选择的源极偏置线和相同数量的字线中的多条选择线，并且可以与字线双向地选择 。 一个字节的单元具有通过相应选择晶体管访问和单独选择的公共源。 在字节擦除阶段期间，通过将施加在控制栅极和组成关于公共接地电位的特定选定字节的单元的各个公共源极区域之间施加的电压分开来获得EEPROM功能，从而减少了EEPROM功能。 在取消细胞上诱导的电应激。

公开(公告)号：USRE35472E

公开(公告)日：1997-03-11

申请号：US192104

申请日：1994-02-04

Applicant: Giulio Frigerio ,  Alessandro Cremonesi

Inventor： Giulio Frigerio ,  Alessandro Cremonesi

IPC: H03M1/14 ,  H03M1/36

CPC classification number: H03M1/144

Abstract: A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

Abstract translation: 高转换速度模数转换器由多个比较单元构成，其在连续步骤中首先确定模数转换的四个最高有效位，然后确定其中最低有效位，其中第一个完成 将四个最高有效位重新转换为模拟，然后从输入信号中减去它们。

公开(公告)号：US5610421A

公开(公告)日：1997-03-11

申请号：US358152

申请日：1994-12-15

Applicant: Claudio Contiero ,  Tiziana Cavioni ,  Stefano Manzini

Inventor： Claudio Contiero ,  Tiziana Cavioni ,  Stefano Manzini

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/105 ,  H01L27/0623 ,  H01L27/0922

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit.The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

Abstract translation: 公开了一种集成电路结构，其中EPROM单元具有通过与用于形成用于包含N沟道MOS晶体管的P区域相同的操作而形成的有源区域，源极和漏极区域通过与所携带的相同的操作形成 以形成所述晶体管的源极和漏极区域，由与进行相同操作形成的N +区域组成的控制电极以形成用于接触掩埋的N +区域的深区域，以及浮栅电极，其由 导电材料通过与集成电路中的MOS晶体管的栅电极相同的操作形成。 因此，可以在混合集成电路中形成EPROM单元，而不需要有意添加的处理步骤。

公开(公告)号：US5602786A

公开(公告)日：1997-02-11

申请号：US389599

申请日：1995-02-16

Applicant: Luigi Pascucci ,  Marco Olivo

Inventor： Luigi Pascucci ,  Marco Olivo

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/789

Abstract: A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bi-dimensional array of memory elements. The column redundancy circuitry comprises a plurality of non-volatile memory registers wherein each register is associated with a respective redundancy column of redundancy memory elements and each register is programmable to store an address of a defective column and an identifying code for identifying the portion of the bi-dimensional array to which the defective column belongs. When being programmed, each non-volatile memory register is supplied with column address signals and with a first subset of row address signals. The column address signals carry the address of a defective column and the first subset of row address signals carry the identifying code. One signal of a second subset of the row address signals is used to select one non-volatile memory register among the plurality of registers such that the defective column address and the identifying code carried by the column address signals and by the first subset of the row address signals are programmed into the selected non-volatile memory register. Using existing column and row address lines to program the redundancy memory registers reduces the need to generate dedicated on-chip signals, thereby minimizing the size of the memory device.

Abstract translation: 一种在用于半导体存储器件的列冗余集成电路中编程冗余寄存器的方法，其具有被分组在一起的存储器元件列，以形成存储器元件的二维阵列的部分。 列冗余电路包括多个非易失性存储器寄存器，其中每个寄存器与冗余存储器元件的相应冗余列相关联，并且每个寄存器可编程以存储缺陷列的地址和识别代码 缺陷列所属的二维阵列。 当被编程时，每个非易失性存储器寄存器被提供有列地址信号和行地址信号的第一子集。 列地址信号携带有缺陷列的地址，并且行地址信号的第一子集携带识别码。 行地址信号的第二子集的一个信号用于选择多个寄存器中的一个非易失性存储器寄存器，使得由列地址信号和列地址信号所携带的识别码和列的第一子集 地址信号被编程到所选的非易失性存储器寄存器中。 使用现有的列和行地址线来编程冗余存储器寄存器减少了生成专用片上信号的需要，从而最小化存储器件的尺寸。