公开(公告)号：US20020119616A1

公开(公告)日：2002-08-29

申请号：US10123507

申请日：2002-04-15

Applicant: STMicroelectronics S.r.I.

Inventor： Livio Baldi ,  Alfonso Maurelli

IPC: H01L021/8234 ,  H01L021/8244

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.

公开(公告)号：US20020106888A1

公开(公告)日：2002-08-08

申请号：US10006923

申请日：2001-12-04

Applicant: STMicroelectronics S.r.I.

Inventor： Omar Vassalli ,  Massimiliano Gullotta

IPC: H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/7682 ,  H01L21/3105

Abstract: A process that includes forming a metal layer on top of a wafer of semiconductor material; forming a mask having an appropriate geometry; defining the metal layer to form conductive lines in the metal layer according to the geometry of the mask; forming, on side walls of the mask a polymeric structure; selectively removing the mask; depositing, on the polymeric structure and on the conductive lines, an insulating material. The polymeric structure, made of an inorganic polymer, forms a nullsupporting bridgenull for the insulating material, preventing the latter from depositing in the gaps between the conductive lines. In these conditions, the gap between two adjacent conductive lines is occupied only by air, which has a very low dielectric constant. This results in a reduced capacitive coupling between the lines themselves.

Abstract translation: 一种方法，包括在半导体材料晶片的顶部上形成金属层; 形成具有适当几何形状的掩模; 限定所述金属层，以根据所述掩模的几何形状在所述金属层中形成导电线; 在所述面具的侧壁上形成聚合物结构; 选择性地去除掩模; 在聚合物结构上和导电线上沉积绝缘材料。 由无机聚合物制成的聚合物结构形成用于绝缘材料的“支撑桥”，防止其沉积在导电线之间的间隙中。 在这些条件下，两个相邻导电线之间的间隙仅由具有非常低介电常数的空气占据。 这导致线路本身之间的电容耦合减小。

公开(公告)号：US20020097605A1

公开(公告)日：2002-07-25

申请号：US10033718

申请日：2001-12-28

Applicant: STMicroelectronics S.r.I.

Inventor： Roberto Ravazzini

IPC: G11C011/34

CPC classification number: G11C16/12 ,  G11C16/08

Abstract: Presented is an EEPROM circuit comprising: a program array of a matrix of EEPROM cells arranged in columns and rows, a data array of a matrix of EEPROM cells arranged in columns and rows, the cells of the program and data array capable of being written, read, and erased; a reference voltage circuit coupled to the program array capable of producing voltages used to write to and erase data from the program array; a current generation circuit coupled to the program array for supplying current to the program array in operation. Advantageously according to the invention, the reference voltage circuit and the current generation circuit are additionally coupled to the data array. Moreover, the EEPROM circuit further comprises means for selectively connecting at least one of the rows of the program array to one of the rows of the data array, and for selectively connecting at least one of the columns of the program array to one of the columns of the data array.

Abstract translation: 提出了一种EEPROM电路，包括：排列成列和行的EEPROM单元的矩阵的程序阵列，排列成列和行的EEPROM单元的矩阵的数据阵列，能够被写入的程序和数据阵列的单元， 阅读和删除; 耦合到所述程序阵列的参考电压电路，其能够产生用于写入和擦除来自所述程序阵列的数据的电压; 耦合到程序阵列的电流产生电路，用于在操作中向程序阵列提供电流。 有利的是，根据本发明，参考电压电路和电流产生电路另外耦合到数据阵列。 此外，EEPROM电路还包括用于选择性地将程序阵列的行中的至少一个连接到数据阵列的行之一的装置，并且用于选择性地将程序阵列的列中的至少一个连接到列之一 的数据数组。

公开(公告)号：US20020088995A1

公开(公告)日：2002-07-11

申请号：US09989318

申请日：2001-11-20

Applicant: STMicroelectronics S.r.I

Inventor： Fabio De Santis

IPC: H01L031/0336

CPC classification number: H03K17/102 ,  H03K3/356113

Abstract: A switching control method for level shifter includes a phase of de-selection of a high voltage value at an output terminal of the shifter using a selection signal. The de-selection phase may include starting the de-selection by bringing the selection signal to a low value; de-activating by way of the selection signal, the generation of a high-voltage signal being supplied to the shifter, and a reference voltage signal; computing the difference between an internal voltage signal of the shifter and the reference voltage signal; generating a control signal when the difference is found to be less than a threshold voltage value; and applying the selection signal to an input terminal of the shifter in the presence of the control signal.

Abstract translation: 电平转换器的切换控制方法包括使用选择信号在移位器的输出端上去选择高电压值的相位。 解除选择阶段可以包括通过使选择信号为低值来开始去选择; 通过选择信号去激活，提供给移位器的高电压信号的产生和参考电压信号; 计算移位器的内部电压信号与参考电压信号之间的差值; 当发现所述差小于阈值电压值时产生控制信号; 以及在存在控制信号的情况下将选择信号施加到移位器的输入端。

公开(公告)号：US20020070397A1

公开(公告)日：2002-06-13

申请号：US09998602

申请日：2001-11-16

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: H01L029/94

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A contact structure for a ferroelectric memory device 13 integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the latter, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises at least a plurality of plugs filled with a nonconductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material for the second conduction terminals or the control circuitry.

Abstract translation: 一种集成在半导体衬底中的铁电存储器件13的接触结构，包括适当的控制电路和铁电存储器单元的矩阵阵列，其中每个单元包括连接到铁电电容器的MOS器件。 MOS器件具有第一和第二导电端子并被绝缘层覆盖。 铁电电容器具有形成在第一导电端子上方的绝缘层上的下板，并且与下一个电极电连接，该下板被一层铁电材料覆盖并电容耦合到上板。 有利地，接触结构包括在第一导电端子和铁电电容器之间填充有非导电材料的至少多个插塞，并且包括填充有用于第二导电端子或控制电路的导电材料的多个插头。

公开(公告)号：US20020056888A1

公开(公告)日：2002-05-16

申请号：US09972766

申请日：2001-10-05

Applicant: STMicroelectronics S.r.I.

Inventor： Riccardo Depetro

IPC: H01L029/00

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

Abstract translation: 一种集成在半导体衬底中的电感结构，包括至少一个与衬底绝缘的导电元件，包括绝缘结构，该绝缘结构形成在所述半导体衬底的内部并靠近所述导体元件构建，使得所述衬底的电阻增加， 由衬底中的导体元件引起的寄生电流减小。 绝缘结构包括多个绝缘元件，每个绝缘元件围绕基板的多个半导体岛的相应一个。

公开(公告)号：US20020034329A1

公开(公告)日：2002-03-21

申请号：US09974290

申请日：2001-10-09

Applicant: STMicroelectronics S.r.I

Inventor： Loris Navoni ,  Roberto Canegallo ,  Mauro Chinosi ,  Giovanni Gozzini ,  Alan Kramer ,  Pierluigi Rolandi

IPC: G06K009/00

CPC classification number: G06F17/30985 ,  G11C15/046 ,  Y10S707/99936

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

公开(公告)号：US20020021582A1

公开(公告)日：2002-02-21

申请号：US09898744

申请日：2001-07-03

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: G11C011/34

CPC classification number: G11C16/08 ,  G11C16/0491 ,  H01L27/115

Abstract: A non-volatile memory matrix architecture, having a virtual ground monolithically integrated on a semiconductor substrate, includes a plurality of memory cells organized into matrix blocks. The matrix blocks are placed on rows and columns and are associated with respective row and column decoding circuits. The memory blocks are separated from each other by at least one insulation stripe which is parallel to the columns. The non-volatile memory matrix architecture further includes a pass-transistor decoding circuit with a number of levels corresponding to the number of rows to select.

Abstract translation: 具有单片集成在半导体衬底上的虚拟接地的非易失性存储矩阵体系包括被组织成矩阵块的多个存储单元。 矩阵块被放置在行和列上并且与相应的行和列解码电路相关联。 存储块通过平行于列的至少一个绝缘条彼此分离。 非易失性存储器矩阵架构还包括具有对应于要选择的行数的多个级别的传输晶体管解码电路。

公开(公告)号：US20010041385A1

公开(公告)日：2001-11-15

申请号：US09899461

申请日：2001-07-05

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Giovanni Cigada ,  Fulvio Silvio Tondelli

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L21/4842 ,  H01L23/49582 ,  H01L24/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/3426 ,  H05K13/0092 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A metal frame patterned by die stamping has the outermost end portion of each patterned pin extending freely, without constraints, from a line of metal bridge connections (dam bar). The end face of each pin is also covered, as well as other surfaces of the frame, by a coating layer or multilayer of metals different from the metal of the die stamped frame. The coating layer or multilayer contains at least on its outer surface, a noble metal such as palladium or gold. The tip of the pins are not subject to cutting and/or trimming after plating the die stamped frame. The pins are not even cut or trimmed during separation of the patterned frame from the surrounding metal at the end of the encapsulation process, when the pins are then eventually bent into shape.

公开(公告)号：US20010033504A1

公开(公告)日：2001-10-25

申请号：US09814176

申请日：2001-03-21

Applicant: STMicroelectronics S.r.I.

Inventor： Ezio Galbiati ,  Maurizio Nessi ,  Marco Palestra

IPC: H02M003/24

CPC classification number: H02M7/53873

Abstract: A feedback control circuit is for the current in a load formed by a winding in series with a current sensing resistor, coupled to a full-bridge output stage, an amplifier coupled to the terminals of the sensing resistor, and a controller fed with the output of the amplifier and with a voltage reference and producing a correction signal. The circuit has a PWM converter for generating a pair of control signals. The PWM converter includes an up/down counter producing a count value and logic circuitry that produces the twos-complement of the correction signal. A pair of registers are coupled to the outputs of the controller and of the logic circuitry. A first comparator coupled to the outputs of the counter and of the first register produces the first control signal, if the count signal exceeds the value stored in the first register. A second comparator coupled to the counter and to the second register produces the second control signal, if the count signal overcomes the value stored in the second register.

Abstract translation: 反馈控制电路用于由负载形成的负载中的电流，该绕组与耦合到全桥输出级的电流感测电阻串联，耦合到感测电阻的端子的放大器和馈送有输出的控制器 并具有电压基准并产生校正信号。 该电路具有用于产生一对控制信号的PWM转换器。 PWM转换器包括产生计数值的上/下计数器和产生校正信号的二进制补码的逻辑电路。 一对寄存器耦合到控制器和逻辑电路的输出端。 如果计数信号超过存储在第一寄存器中的值，则耦合到计数器和第一寄存器的输出的第一比较器产生第一控制信号。 如果计数信号克服存储在第二寄存器中的值，则耦合到计数器和第二寄存器的第二比较器产生第二控制信号。