公开(公告)号：US20240193795A1

公开(公告)日：2024-06-13

申请号：US18535429

申请日：2023-12-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Marina Nicolas

IPC: G06T7/246 ,  G06T7/12 ,  G06T7/136 ,  G06T7/215

CPC classification number: G06T7/248 ,  G06T7/12 ,  G06T7/136 ,  G06T7/215 ,  G06T2207/10016 ,  G06V20/41

Abstract: The present description concerns a system and method of determining at least one classifier of a general movement along a first direction in video images of a scene, comprising determining a differential image based on two video images, selecting pixels of the differential image corresponding to edges of objects, determining, for each selected pixel, at least one classifier of a local movement along the first direction at least at a first or second value, determining a first indicator of the local movement along the first direction, which depends on the sum of the local movement classifiers at the first value and a second indicator of the local movement along the first direction, which depends on the sum of the local movement classifiers at the second value, and determining the general movement classifier based on the comparison of the first and second local movement indicators.

公开(公告)号：US12001259B2

公开(公告)日：2024-06-04

申请号：US17081319

申请日：2020-10-27

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Lemarchand ,  Pierre-Loic Felter ,  Darin K Winterton ,  Kalyan-Kumar Vadlamudi-Reddy

IPC: G06F1/3231 ,  G01S7/41 ,  G01S13/56

CPC classification number: G06F1/3231 ,  G01S7/415 ,  G01S13/56

Abstract: In accordance with embodiments, methods and systems for utilizing multiple threshold checkers are provided. A range sensor collects measurement data. The range sensor examines the measurement data based on multiple threshold checkers to determine satisfaction of a trigger condition. In response to the satisfaction of the trigger condition, the range sensor provides the measurement data to a host computing device of the range sensor.

公开(公告)号：US11984796B2

公开(公告)日：2024-05-14

申请号：US17677806

申请日：2022-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Vratislav Michal

IPC: H02M3/07 ,  H02M1/00

CPC classification number: H02M1/0095 ,  H02M3/07

Abstract: In an embodiment a power converter includes a first capacitor and a second capacitor coupled in series with the first capacitor, wherein the converter is configured to charge, during a first phase, the first and second capacitors by a supply voltage so that a voltage across terminals of each of the first and second capacitors is substantially equal to half the supply voltage and discharge, during a second phase, the second capacitor to a third capacitor.

公开(公告)号：US11984373B2

公开(公告)日：2024-05-14

申请号：US17522327

申请日：2021-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Lopez

IPC: H01L23/31 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52 ,  H01S5/02218 ,  H01S5/068

CPC classification number: H01L23/3114 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

公开(公告)号：US20240134406A1

公开(公告)日：2024-04-25

申请号：US18379262

申请日：2023-10-11

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Julien GOULIER ,  Nicolas GOUX ,  Marc JOISSON

IPC: G05F3/26 ,  G05F1/46 ,  H03K17/18 ,  H03K17/22

CPC classification number: G05F3/262 ,  G05F1/468 ,  H03K17/18 ,  H03K17/22 ,  H03F3/45179

Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.

公开(公告)号：US11960718B2

公开(公告)日：2024-04-16

申请号：US17721933

申请日：2022-04-15

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS S.r.l.

Inventor： Leonardo Valencia Rissetto ,  Francesco Tomaiuolo ,  Diego De Costantini

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.

公开(公告)号：US11935992B2

公开(公告)日：2024-03-19

申请号：US17965443

申请日：2022-10-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Remi Brechignac ,  Jean-Michel Riviere

IPC: H01L33/52 ,  H01L31/0203 ,  H01L31/0216 ,  H01L33/44 ,  H01L33/62

CPC classification number: H01L33/52 ,  H01L31/0203 ,  H01L31/02164 ,  H01L33/44 ,  H01L33/62

Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.

公开(公告)号：US11923256B2

公开(公告)日：2024-03-05

申请号：US17378398

申请日：2021-07-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Olivier Franiatte ,  Richard Rembert

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/04 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603

CPC classification number: H01L23/04 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/5385 ,  H01L2021/60022 ,  H01L21/603

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

公开(公告)号：US20240046889A1

公开(公告)日：2024-02-08

申请号：US18492066

申请日：2023-10-23

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Maucotel

IPC: G09G3/34 ,  G09G5/10

CPC classification number: G09G3/3406 ,  G09G5/10 ,  G01J2001/4238

Abstract: An electronic system includes a control circuit to provide a binary control signal alternating between a first binary state during first phases and a second binary state during second phases; a screen controlled by the control signal, the screen emitting light during each first phase, and to not emit any light during each second phase; a light sensor under the screen or along the edge of the screen, and providing a measurement signal representative of a quantity of light received by the sensor during a measurement phase or a plurality of consecutive measurement phases; and a synchronization device to synchronize each measurement phase with a second phase.

公开(公告)号：US11892568B2

公开(公告)日：2024-02-06

申请号：US17074238

申请日：2020-10-19

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Ivelina Hristova ,  Pascal Mellot ,  Neale Dutton

IPC: G06T7/50 ,  G06F1/10 ,  G06T15/08 ,  G06T15/00 ,  G01S7/4865 ,  G01S17/894 ,  G01S7/4863

CPC classification number: G01S7/4865 ,  G01S7/4863 ,  G01S17/894 ,  G06F1/10 ,  G06T7/50 ,  G06T15/005 ,  G06T15/08 ,  G06T2207/10108

Abstract: A depth map sensor includes a first array of first pixels, each first pixel having a first photodetector associated with a pixel circuit that comprises a plurality of first bins for accumulating events. A clock source is configured to generate a plurality of phase-shifted clock signals. A first circuit has a plurality of first output lines coupled to the first array of first pixels. The first circuit is configured to receive the plurality of phase-shifted clock signals. The first circuit includes a first block and a second block. The first block is configured to propagate the plurality of phase-shifted clock signals to the second block during a first period determined by a first enable signal and the second block configured to select to which of the plurality of first output lines each of the plurality of phase-shifted clock signals is applied.