公开(公告)号：US20060137449A1

公开(公告)日：2006-06-29

申请号：US11024191

申请日：2004-12-28

Applicant: Joseph McAlexander

Inventor： Joseph McAlexander

IPC: G01P15/00

CPC classification number: H01H35/14 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81C1/0015 ,  G01P15/0802 ,  G01P15/0891 ,  G01P15/125 ,  G01P15/135 ,  G01P2015/0828 ,  H01H1/0036

Abstract: A released-beam sensor includes a semiconductor substrate having a layer formed thereon, and an aperture formed in the layer. A beam is mechanically coupled at a first end to the layer and suspended above the layer such that a second end forms a cantilever above the aperture. A boss is coupled to a second end of the beam and suspended at least partially within the aperture. The beam is configured to flex in response to acceleration of the substrate along a vector substantially perpendicular to a surface of the substrate. Parameters of the sensor, such as the dimensions of the beam, the mass of the boss, and the distance between the boss and a contact surface within the aperture, are selected to establish an acceleration threshold at which the boss will make contact with the contact surface. The sensor may be employed to deploy an airbag in a vehicle.

Abstract translation: 释放光束传感器包括其上形成有层的半导体衬底和形成在该层中的孔。 梁在第一端机械耦合到层并且悬挂在层上方，使得第二端在孔的上方形成悬臂。 凸台联接到梁的第二端并至少部分地悬挂在孔内。 梁被构造成响应于基板垂直于基板的表面的矢量的加速度而弯曲。 选择传感器的参数，例如梁的尺寸，凸台的质量以及凸台和孔内的接触表面之间的距离，以建立凸台将与触点接触的加速度阈值 表面。 可以使用传感器将气囊展开在车辆中。

公开(公告)号：US07057843B2

公开(公告)日：2006-06-06

申请号：US10447913

申请日：2003-05-28

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: G11B5/596

CPC classification number: G11B5/59605

Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

Abstract translation: 伺服控制电路提供搜索和跟踪模式之间的无缝转换，同时实现快速寻道模式操作和精确跟踪。 控制电路包括具有非线性特性的模数转换器。 非线性特性提供不成比例的大的控制电压，以在寻轨模式下导出速度和稳定，并且在轨道模式中提供基本上线性的控制电压，以提供低噪声和准确的跟踪操作。

公开(公告)号：US20060091920A1

公开(公告)日：2006-05-04

申请号：US10978852

申请日：2004-11-01

Applicant: Tom Youssef

Inventor： Tom Youssef

IPC: H03L7/00

CPC classification number: H03K3/356008 ,  H03K17/223

Abstract: A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state. A resistive divider circuit, including at least two resistors connected in series with each other at a tap, is connected in series with the source-drain circuit of the static current control transistor. The tap of the resistive divides circuit is connected to the input node of the pulse generation circuit to supply the flip signal.

公开(公告)号：US07028164B2

公开(公告)日：2006-04-11

申请号：US09751679

申请日：2000-12-29

Applicant: Anthony X. Jarvis ,  Mark Owen Homewood ,  Gary L. Vondran

Inventor： Anthony X. Jarvis ,  Mark Owen Homewood ,  Gary L. Vondran

IPC: G06F9/40

CPC classification number: G06F9/3816 ,  G06F9/30149

Abstract: There is disclosed a data processor containing an instruction issue unit that efficiently transfers instruction bundles from a cache to an instruction pipeline. The data processor comprises 1) an instruction pipeline comprising N processing stages; and 2) an instruction issue unit for fetching into the instruction pipeline instructions fetched from the instruction cache, each of the fetched instructions comprising from one to S syllables. The instruction issue unit comprises: a) a first buffer comprising S storage locations for storing up to S syllables associated with the fetched instructions, each of the S storage locations storing one of the one to S syllables of each fetched instruction; b) a second buffer comprising S storage locations for storing up to S syllables associated with the fetched instructions, each of the S storage locations for storing one of the one to S syllables of each fetched instruction; and c) a controller for determining if a first one of the S storage locations in the first buffer is full, wherein the controller, in response to such a determination, stores a corresponding syllable in an incoming fetched instruction in one of the S storage locations in the second buffer.

公开(公告)号：US07027247B2

公开(公告)日：2006-04-11

申请号：US09993778

申请日：2001-11-05

Applicant: Fereidoon Heydari ,  Hakan Ozdemir ,  Sadik O. Arf

Inventor： Fereidoon Heydari ,  Hakan Ozdemir ,  Sadik O. Arf

IPC: G11B5/09 ,  G11B27/36

CPC classification number: G11B5/59633

Abstract: A new synchronous Partial Response Maximum Likelihood (PRML) servo is provided for a high track-per-inch disk-drive system. To increase the data capacity in hard disk drives (HDD), one can shorten the servo format and/or increase the track density. The new servo system has circuits that allow a high-performance and accurate system for positioning the read-write heads. The major circuits include burst demodulation, Viterbi detection, timing synchronization, and spin-up search. A highly linear discrete-fourier-transform (DFT) burst-demodulation circuit can demodulate high-density and low-signal-to-noise-ratio (SNR) position bursts. The Viterbi detection circuit includes a sync-mark detector and a Viterbi detector that are matched to at least two sets of Gray code ( e.g., ¼ rate and 4/12 rate) and pruned accordingly. The timing synchronization circuit includes phase restart and interpolating timing recovery (ITR) circuits to implement a fully digital timing recovery. The spin-up search circuit may include a robust multistage search circuit that detects a preamble and/or a DC field to search for an initial servo sector with a low error rate during spin up. In one example, the servo system samples each dibit 4 times throughout the entire servo sector uses PR4 equalization. The relatively low number of samples required for the system allows the servo format density to be near the channel bandwidth while increasing the SNR performance.

公开(公告)号：US07026718B1

公开(公告)日：2006-04-11

申请号：US09160824

申请日：1998-09-25

Applicant: Tsiu Chiu Chan ,  Arnaud Lepert ,  Lawrence Philip Eng

Inventor： Tsiu Chiu Chan ,  Arnaud Lepert ,  Lawrence Philip Eng

IPC: H01L23/48

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method for fabricating-a microprocessor comprising a first chip (12) having an active face (30) including a central processing unit and a second chip (14) having an active face (32) electrically connected to the active face of the first chip (12), wherein the second chip (14) provides added functionality to the central processing unit of the first chip (12) and wherein the electrical connections (16, 18) are through bonding layers (28) that are in contact with the metalization 26 on the first and second chips (12, 14), is disclosed.

Abstract translation: 一种用于制造微处理器的装置和方法，包括具有主动面（30）的第一芯片（12），所述主动面包括中央处理单元和第二芯片（14），所述主动面具有电连接到所述主动面 第一芯片（12），其中所述第二芯片（14）向所述第一芯片（12）的中央处理单元提供附加功能，并且其中所述电连接（16,18）通过与 公开了第一和第二芯片（12,14）上的金属化26。

公开(公告)号：US20060002180A1

公开(公告)日：2006-01-05

申请号：US10880980

申请日：2004-06-30

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C11/00

CPC classification number: G06F11/1076 ,  G11C7/1006 ,  G11C11/16 ,  G11C16/10 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.

Abstract translation: 随机存取存储器阵列包括以多个行和列排列的用于在多个存储器位置存储数据字的第一随机存取存储器元件。 存储器阵列还包括布置在至少一个附加列中的第二随机存取存储器元件。 每个第二随机存取存储器元件与存储器位置相关联，以存储指示存储在该存储器位置的数据字是真还是补补版本的标志值。 各个存储元件可以包括磁性随机存取存储器元件。 或者，各个存储元件可以包括闪存单元。

公开(公告)号：US20060001469A1

公开(公告)日：2006-01-05

申请号：US10881098

申请日：2004-06-30

Applicant: Roberto La Rosa

Inventor： Roberto La Rosa

IPC: H03F3/04

CPC classification number: H03F1/56 ,  H03H11/52

Abstract: Variations in the actual resistance of a target poly resistor in a semiconductor integrated circuit can be compensated for by using an active circuit that provides a negative resistance in parallel with the target resistor. This produces a tuned resistance that is closer to a desired resistance than is the actual resistance of the target resistor.

公开(公告)号：US06975696B1

公开(公告)日：2005-12-13

申请号：US11076785

申请日：2005-03-10

Applicant: Naren K. Sahoo

Inventor： Naren K. Sahoo

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06M3/00

CPC classification number: G01R31/318527 ,  G01R31/31727 ,  G01R31/3187

Abstract: A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of counters has a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over. A comparison circuit having inputs coupled to the first and second counter outputs, compares the first and second counter outputs to produce a counter error output signal. A latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs. Counters may be segmented to reduce a number of digits.

Abstract translation: 集成电路中的计数器系统的自检包括耦合到多个计数器中的计数器的时钟。 多个计数器中的第一计数器具有第一计数器输出和第一计数器翻转。 多个计数器中的第二计数器具有第二计数器输出，小于第一计数器翻转的第二计数器翻转以及当第二计数器翻转时有效的第二计数器翻转信号。 具有耦合到第一和第二计数器输出的输入的比较电路，比较第一和第二计数器输出以产生计数器误差输出信号。 响应于第二计数器翻转信号不活动并且计数器错误输出信号指示第一和第二计数器输出的差异，锁存器锁存计数器错误输出信号。 可以对计数器进行分段以减少数位数。

公开(公告)号：US06970316B2

公开(公告)日：2005-11-29

申请号：US09991557

申请日：2001-11-09

Applicant: Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

Inventor： Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B15/12

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit includes switching circuitry connected between the terminals of the write head and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry that generates control signals for controlling the switching circuitry.

Abstract translation: 公开了一种电路和方法，用于相对快速地使流过写入头的电流在稳态之间转变而不产生可观量的电容耦合噪声。 本发明的实施例通常向写入头提供在写入头中的稳态电流电平之间的转换期间不具有共模电压电平的驱动电压信号。 换句话说，施加到写入头的驱动电压信号在写入头电流转换期间基本上完全不同。 在本发明的示例性实施例中，驱动器电路包括连接在写入头的端子和参考电压源（例如正和负电压源）之间的开关电路。 驱动器电路还包括产生用于控制开关电路的控制信号的定时电路。