公开(公告)号：US20070236205A1

公开(公告)日：2007-10-11

申请号：US11680586

申请日：2007-02-28

Applicant: Osvaldo Zambetti ,  Alessandro Zafarana

Inventor： Osvaldo Zambetti ,  Alessandro Zafarana

IPC: B23K11/24

CPC classification number: H02M3/156 ,  H02M3/1584

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs by detecting the derivative of a voltage signal of the output terminal. All the phases of the converter are simultaneously driven by zeroing a driving interleaving phase shift on the basis of the detected load transient, and the driving interleaving phase shift is recovered to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract translation: 提供了一种用于控制多相交错类型的转换器的方法。 根据该方法，通过检测输出端子的电压信号的导数来检测施加到转换器的输出端子的负载变化。 转换器的所有相位同时通过基于检测到的负载瞬变归零驱动交错相移而被驱动，并且驱动交错相移被恢复以重新开始转换器的正常操作。 还提供了一种用于执行这种方法的控制器。

公开(公告)号：US20070229049A1

公开(公告)日：2007-10-04

申请号：US11680581

申请日：2007-02-28

Applicant: Alessandro Zafarana ,  Osvaldo Zambetti

Inventor： Alessandro Zafarana ,  Osvaldo Zambetti

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M3/1584

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs. All the phases of the converter are simultaneously turned off, and a driving interleaving phase shift is recovered so as to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract translation: 提供了一种用于控制多相交错类型的转换器的方法。 根据该方法，检测何时发生对转换器的输出端子施加的负载的变化。 转换器的所有相同时关断，并且恢复驱动交错相移，以重新开始转换器的正常操作。 还提供了一种用于执行这种方法的控制器。

公开(公告)号：US20070198669A1

公开(公告)日：2007-08-23

申请号：US11671773

申请日：2007-02-06

Applicant: Gabriella Convertino ,  Fabrizio Crudo ,  Antonio Vilei

Inventor： Gabriella Convertino ,  Fabrizio Crudo ,  Antonio Vilei

IPC: G06F15/177

CPC classification number: H04L12/2807 ,  H04L65/601 ,  H04L65/604 ,  H04L2012/2841 ,  H04L2012/2849

Abstract: A device of a plug-and-play type, which can be integrated in a home network having at least one audio-video Media-Server device or else at least one audio-video Media-Renderer device. The device can be activated for selectively configuring parameters and devices for setting up audio-video calls for connection between the home network and a packet network, such as the Internet. Preferentially, the device is based upon UPnP (Universal Plug-and-Play) technology and uses either a signaling protocol on IP packet network, such as the Session Initiation Protocol (SIP) and ITU-T H.323, or else mobile communications systems, such as the Universal Mobile Telecommunications System (UMTS). The device is able to redirect audio-video streams in the context of a plurality of devices capable of reproducing them and/or to selectively acquire said audio-video streams from a plurality of devices capable of supplying them.

Abstract translation: 一种即插即用类型的设备，其可集成在具有至少一个音频 - 视频媒体服务器设备或至少一个音频 - 视频媒体呈现器设备的家庭网络中。 可以激活该设备以选择性地配置用于设置用于家庭网络和分组网络（例如因特网）之间的连接的音频 - 视频呼叫的参数和设备。 优选地，该设备基于UPnP（通用即插即用）技术，并且在诸如会话发起协议（SIP）和ITU-T H.323之类的IP分组网络上使用信令协议，或者使用移动通信系统 ，例如通用移动电信系统（UMTS）。 该设备能够在能够再现它们的多个设备的上下文中重定向音频 - 视频流，和/或从能够提供它们的多个设备中选择性地获取所述音频 - 视频流。

公开(公告)号：US20070126064A1

公开(公告)日：2007-06-07

申请号：US11605190

申请日：2006-11-27

Applicant: Fabio Pellizzer ,  Paolo Cappelletti

Inventor： Fabio Pellizzer ,  Paolo Cappelletti

IPC: H01L31/00

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/0705

Abstract: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

Abstract translation: 集成晶体管器件形成在半导体材料的芯片中，其具有限定容纳垂直型双极晶体管的有源区域的电绝缘区域和彼此相邻的平面型MOSFET。 活动区域容纳收集区域; 与集电极区域相邻的双极基极区域; 在双极基区内的发射极区; 源极区域，布置在距离双极基极区域一定距离处; 漏区; 布置在源极区域和漏极区域之间的沟道区域; 和一个井区。 漏极区域和双极基极区域是连续的，并且形成由双极晶体管和MOSFET共享的公共基极结构。 因此，集成晶体管器件具有高输入阻抗并且能够驱动高电流，同时仅需要小的积分面积。

公开(公告)号：US20070115743A1

公开(公告)日：2007-05-24

申请号：US11530199

申请日：2006-09-08

Applicant: Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

Inventor： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

IPC: G11C7/00

CPC classification number: G06F13/4282 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/30

Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

Abstract translation: 存储器架构包括包括命令集的存储器和用于将存储器连接到通用主机设备的串行外设接口（SPI）。 SPI包括用于从主机设备向存储器的输入提供输出数据的数据; 用于将输出数据从存储器提供给主机设备的输入的数据输出线; 由主机设备驱动的时钟线; 以及允许主机设备打开和关闭存储器的启用行。 内存是一个NAND闪存。 SPI包括一个I / O寄存器块，包括一个SPI标签寄存器和一个数据寄存器，用于分别从相应的SPI标签寄存器驱动指向存储器的数据，命令和地址。

公开(公告)号：US20070085522A1

公开(公告)日：2007-04-19

申请号：US11548996

申请日：2006-10-12

Applicant: Adalberto MARIANI ,  Silvio Pepino

Inventor： Adalberto MARIANI ,  Silvio Pepino

IPC: G05F1/00

CPC classification number: H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A control device for a switching converter has an input terminal and an output terminal; the converter includes a half-bridge of a first and a second transistor coupled between the input terminal and a reference voltage. The control device detects a signal on the output terminal of the converter, integrates the detected signal and imposes a predefined minimum frequency of the detected signal. The control device regulates the average value of the detected signal by comparison with a reference signal and drives the first and second transistors in during the regulation. The control device turns off an integrator when the predefined minimum frequency is imposed.

Abstract translation: 用于开关转换器的控制装置具有输入端和输出端; 该转换器包括耦合在输入端和参考电压之间的第一和第二晶体管的半桥。 控制装置检测转换器的输出端子上的信号，对检测到的信号进行积分并施加预定的检测信号的最小频率。 控制装置通过与参考信号进行比较来调节检测信号的平均值，并在调节期间驱动第一和第二晶体管。 当施加预定的最小频率时，控制装置关闭积分器。

公开(公告)号：US20070067115A1

公开(公告)日：2007-03-22

申请号：US11519425

申请日：2006-09-11

Applicant: Roberto Canegallo ,  Mauro Mirandola ,  Alberto Fazzi ,  Luca Magagni ,  Roberto Guerrieri

Inventor： Roberto Canegallo ,  Mauro Mirandola ,  Alberto Fazzi ,  Luca Magagni ,  Roberto Guerrieri

IPC: G01F23/00

CPC classification number: G01R31/2891 ,  G01R31/312 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, comprising a multiple-capacitor structure integrated in said capacitive sensor, at least a sensing circuit connected to said multiple-capacitor structure which issues an output voltage, proportional to a variation of a capacitive value of the multiple-capacitor structure of the integrated capacitive sensor of the device and corresponding to a measured misalignment between the chips of the device.

Abstract translation: 本发明的实施例涉及一种用于测量装置的多个芯片之间的对准的对准测量系统，所述芯片被组装成三维堆叠配置并且装备有至少一个集成电容式传感器，所述集成电容传感器包括多电容器 集成在所述电容传感器中的结构，至少一个连接到所述多电容器结构的感测电路，其发出与设备的集成电容传感器的多电容结构的电容值的变化成比例的输出电压，并且对应于 测量的器件芯片之间的未对准。

公开(公告)号：US20070038966A1

公开(公告)日：2007-02-15

申请号：US11482513

申请日：2006-07-07

Applicant: Gianfranco Cerofolini ,  Danilo Mascolo

Inventor： Gianfranco Cerofolini ,  Danilo Mascolo

IPC: G06F17/50

CPC classification number: H01L21/76816 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/70916 ,  G11C2213/81 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with insulating nanowires. Each realization of a conductive nanowire fills a corresponding recess by a respective elbow-like portion of the conductive nanowire, and partially fills the other recesses by respective notched profile portions, thereby forming the nanometric circuit. The method forms, above the nanometric circuit, an insulating layer; opens, in the insulating layer, n windows respectively corresponding with the recesses, thereby exposing the respective elbow-like portions; and realizes, above the insulating layer, n conductive dies addressed towards the standard electronic components and respectively overlapping the windows, thereby forming n contacts realizing the electric connection.

Abstract translation: 一种方法实现了纳米电路和标准电子部件之间的电连接。 该方法包括：在半导体衬底之上提供具有基本上垂直于衬底的切口壁的种子，所述壁具有彼此间隔开的n个凹槽; 并实现与绝缘纳米线交替的n导电纳米线。 导电纳米线的每个实现都由导电纳米线的相应肘形部分填充相应的凹部，并且通过相应的凹口轮廓部分部分地填充其它凹部，从而形成纳米线。 该方法在纳米电路上形成绝缘层; 在绝缘层中打开分别对应于凹部的n个窗口，从而暴露相应的弯头状部分; 并且在绝缘层之上实现n个导电模，其朝着标准电子部件寻址并分别与窗重叠，从而形成实现电连接的n个触点。

公开(公告)号：US20060278900A1

公开(公告)日：2006-12-14

申请号：US11312233

申请日：2005-12-19

Applicant: Kuo-Wei Chang ,  Jong-Won Lee ,  Paola Besana

Inventor： Kuo-Wei Chang ,  Jong-Won Lee ,  Paola Besana

IPC: H01L29/768

CPC classification number: H01L45/04 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16

Abstract: A memory includes a phase change memory element having a memory layer of a calcogenide material and a glue layer of an alloy of the form TiaXbNc where X is selected in the group comprising silicon, aluminum, carbon, or boron, and c may be 0. The nitrogen and silicon are adapted to reduce the diffusion of titanium toward the chalcogenide layer.

Abstract translation: 存储器包括相变存储元件，该相变存储元件具有硫化物质材料的存储层和形式为Ti x N b N c C的合金的胶层， / SUB>其中X选自硅，铝，碳或硼，c可以为0.氮和硅适于减少钛向硫族化物层的扩散。

公开(公告)号：US20060259847A1

公开(公告)日：2006-11-16

申请号：US11411010

申请日：2006-04-25

Applicant: Corrado Villa

Inventor： Corrado Villa

IPC: H03M13/00

CPC classification number: G06F11/1068

Abstract: An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A first error correction code associated with the datum is stored in the M cells along with a first enable bit or guard-cell which is indicative of whether the first error correction code is active. The number of M cells, adjacent to the N cells of the row, is defined on the basis of the number N of cells. In the event the datum stored in the first portion of the N cells of the row is subsequently updated or manipulated, a second error correction code associated with the updated or manipulated datum is determined and stored in the second portion of the N cells of the row along with a second enable bit or guard-cell which is indicative of whether the second error correction code is active. At that point, the first enable bit or guard-cell is modified to indicate that the first error correction code is not active.

Abstract translation: 非易失性存储单元的阵列包括具有N个单元和M个单元的行。 在部分存储步骤中，将数据存储在行的N个单元的第一部分中。 该行的N个单元的第二部分处于“擦除”状态。 与数据相关联的第一纠错码与第一使能位或保护单元一起存储在M个单元中，第一使能位或保护单元指示第一纠错码是否有效。 基于单元数N来定义与行的N个单元相邻的M个单元的数量。 在存储在行的N个单元的第一部分中的数据随后被更新或操作的情况下，确定与更新或操纵的数据相关联的第二纠错码并存储在该行的N个单元的第二部分中 以及指示第二纠错码是否有效的第二使能位或保护单元。 此时，修改第一使能位或保护单元以指示第一纠错码未被激活。