公开(公告)号：US20240331762A1

公开(公告)日：2024-10-03

申请号：US18428992

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： William Charles Filipiak ,  Huai-Yuan Tseng

IPC: G11C11/4096 ,  G06F7/544 ,  G11C11/408

CPC classification number: G11C11/4096 ,  G06F7/5443 ,  G11C11/4085

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of the memory cell array is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, memory cell conditions related to data retention stress, quick charge loss, back-pattern effects, and/or cross-temperature variations. Based on the determined context, the controller dynamically determines adjustments to wordline and/or other memory cell bias voltages used during the multiplication.

公开(公告)号：US20240329867A1

公开(公告)日：2024-10-03

申请号：US18584993

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Yee Yang Tay ,  Lei Zhang ,  Steve Kientz ,  Edric Goh

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0679

Abstract: Methods, apparatuses and systems related to tracking charge loss are described. An apparatus may include a tracking mechanism configured to make direct measurements for tracking charge loss in first-type cells. The apparatus may be configured to designate a set of the first-type cells as proxy for modeling charge loss at second-type cells having a different storage density than the first-type cells. The apparatus may use the tracking mechanism to make measurements on the proxy set of the first-type cells and translate the measurement to account for the charge loss at the second-type cells.

公开(公告)号：US20240329852A1

公开(公告)日：2024-10-03

申请号：US18739982

申请日：2024-06-11

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Charles See Yeung Kwong ,  Vamsi Pavan Rayaprolu ,  Seungjune Jeon ,  Zhenming Zhou

IPC: G06F3/06 ,  G06N20/00

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G06N20/00

Abstract: A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.

公开(公告)号：US20240329840A1

公开(公告)日：2024-10-03

申请号：US18607026

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Giorgio Servalli ,  Marcello Mariani

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: Methods, systems, and devices for memory array configuration for shared word lines are described. A memory array of a memory device may include shared (e.g., shorted) word lines. The memory array may include multiple memory cells, word lines, rows of transistors, and digit lines. Each transistor of the rows of transistors may be coupled with a respective memory cell and includes a connection between a first word line, a second word line, and a gate terminal of a transistor. Additionally, each digit line may be coupled with respective terminals of respective transistors of alternating rows of transistors including a first subset of alternating rows and a second subset of alternating rows that are exclusive from each other. The transistors may be configured according to a first configuration including two digit lines overlapping each transistor or a second configuration including a single digit line overlapping each transistor.

公开(公告)号：US12106813B2

公开(公告)日：2024-10-01

申请号：US17733460

申请日：2022-04-29

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Avinash Rajagiri ,  Devin Batutis

IPC: G11C29/02 ,  G06F11/07 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/02 ,  G06F11/073 ,  G11C29/006 ,  G11C2029/0403

Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

公开(公告)号：US12106099B2

公开(公告)日：2024-10-01

申请号：US18377804

申请日：2023-10-08

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/448 ,  G06F15/78

CPC classification number: G06F9/30018 ,  G06F9/30065 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/3824 ,  G06F9/4498 ,  G06F15/7867

Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an asynchronous packet network having a plurality of data transmission lines forming a data path transmitting operand data; a synchronous mesh communication network; a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the asynchronous packet network and to the synchronous mesh communication network, each configurable circuit of the plurality of configurable circuits adapted to perform a plurality of computations; each configurable circuit of the plurality of configurable circuits comprising: a memory storing operand data; and an execution or write mask generator adapted to generate an execution mask or a write mask identifying valid bits or bytes transmitted on the data path or stored in the memory for a current or next computation.

公开(公告)号：US12105974B2

公开(公告)日：2024-10-01

申请号：US18173466

申请日：2023-02-23

Applicant: Micron Technology, Inc.

Inventor： Kumar V K H Kanteti

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes integrated circuit (IC) dice and a processing device that retrieves a first block group to be written to the IC dice, the first block group being a contiguous portion of a file and associated with a first stream ID. In response to determining there is allocable space available in a first group of memory cells assigned to the first stream ID, identify a write pointer of the first group and allocate, within the first group, a contiguous range of physical addresses beyond the write pointer to which to write the first block group. The processing device retrieves a second block group to be written to the IC dice, the second block group associated with a second file, allocates the second block group to a second group of the memory cells, and assigns a second stream ID associated with the second group to the second block group.

公开(公告)号：US12105971B2

公开(公告)日：2024-10-01

申请号：US17713652

申请日：2022-04-05

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Niccolò Izzo

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices related to determining whether a target address of a memory array associated with an access request is stored in a CAM. If the target address is stored in the CAM, the CAM may be updated to increment an access count of a target row corresponding to the target address. If the target row exceeds a first threshold value, rows of the memory array directly adjacent to the target row may be refreshed. If the target address is not stored in the CAM, the target address may be written to the CAM. The CAM may be updated to increment an access count of an address of a bank including the target row corresponding to the target address.

公开(公告)号：US12105675B2

公开(公告)日：2024-10-01

申请号：US17005671

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Olivier Duval

IPC: G06F16/00 ,  G06F11/14 ,  G06F12/02 ,  G06F16/16 ,  G06F16/17 ,  G06F16/18

CPC classification number: G06F16/1734 ,  G06F11/1407 ,  G06F11/1435 ,  G06F12/0246 ,  G06F16/164 ,  G06F16/1873

Abstract: A processing device writes file system data to a first area of a memory zone of a zoned block memory device based on a current position of a write pointer within the memory zone. The file system data comprises data files contained within a file system and file structure metadata describing a file structure of the file system. The processing device detects a write event based on the write pointer advancing past a predetermined memory address within the memory zone that corresponds to a checkpoint. The checkpoint is a second area within the memory zone that is designated for storing write event data. Based on detecting the write event, the processing device writes write event data to the checkpoint, the first write event data indicating a most recent memory address of a root node of the file structure within the memory zone.

公开(公告)号：US20240321368A1

公开(公告)日：2024-09-26

申请号：US18671835

申请日：2024-05-22

Applicant: Micron Technology, Inc.

Inventor： Tommaso Vali ,  Agostino Macerola

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/3404

Abstract: A memory device includes a memory array comprising a plurality of wordlines, and control logic, operatively coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of wordlines of the memory array and determines respective threshold voltages stored in a number of memory cells associated with each of the plurality of wordlines. The control logic further determines a difference in the respective threshold voltages based on a location of the number of memory cells within each wordline and determines a respective resistance-capacitance (RC) time constant for each of the plurality of wordlines in view of the difference in the respective threshold voltages.