公开(公告)号：US12123910B2

公开(公告)日：2024-10-22

申请号：US18146543

申请日：2022-12-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01R31/317 ,  G01M11/00 ,  G02B6/12 ,  G02B6/27 ,  G02B6/28 ,  G02B6/293 ,  G02F1/21 ,  H01L25/16

CPC classification number: G01R31/31728 ,  G01M11/00 ,  G01M11/332 ,  G01M11/335 ,  G02B6/12004 ,  G02B6/2773 ,  G02B6/2813 ,  G02B6/29332 ,  G02F1/21 ,  G02F1/217 ,  H01L25/167 ,  G02B2006/12147

Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

公开(公告)号：US12063775B2

公开(公告)日：2024-08-13

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US12048257B2

公开(公告)日：2024-07-23

申请号：US18296331

申请日：2023-04-05

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Philippe Reynard ,  Sylvie Del Medico ,  Philippe Brun

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/011 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/231 ,  H10N70/826

Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.

公开(公告)号：US12035643B2

公开(公告)日：2024-07-09

申请号：US17488026

申请日：2021-09-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Yann Canvel ,  Sebastien Lagrasta ,  Sebastien Barnola ,  Christelle Boixaderas

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828

Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

公开(公告)号：US12019293B2

公开(公告)日：2024-06-25

申请号：US17932623

申请日：2022-09-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Francois Carpentier ,  Charles Baudot

IPC: G02B6/43 ,  G02B6/12 ,  G02B6/13 ,  G02B6/42

CPC classification number: G02B6/43 ,  G02B6/12004 ,  G02B6/13 ,  G02B6/4234 ,  G02B2006/12061

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

公开(公告)号：US20240204017A1

公开(公告)日：2024-06-20

申请号：US18591950

申请日：2024-02-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael FOUREL ,  Laurent-Luc CHAPELON

IPC: H01L27/146 ,  G02B1/10 ,  G02B1/14 ,  G02B3/00

CPC classification number: H01L27/14621 ,  G02B1/10 ,  G02B1/14 ,  G02B3/0012 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

公开(公告)号：US20240194815A1

公开(公告)日：2024-06-13

申请号：US18588656

申请日：2024-02-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Denis RIDEAU ,  Dominique GOLANSKI ,  Alexandre LOPEZ ,  Gabriel MUGNY

IPC: H01L31/107 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L31/186

Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

公开(公告)号：US20240192053A1

公开(公告)日：2024-06-13

申请号：US18524960

申请日：2023-11-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Cedric Tubert ,  Matteo Maria Vignetti

IPC: G01J1/44

CPC classification number: G01J1/44 ,  G01J2001/446

Abstract: An embodiment light sensor includes an array of pixels arranged in rows and in columns. Each pixel comprises a photodiode, a sense node coupled to the photodiode, and an initialization transistor connected to the sense node. N successive pixels of a column or of a row are associated, where N is greater than or equal to 2. The initialization transistor of a first one of the pixels arranged at one end of the association of the N pixels is connected between the sense node of the first one of the pixels and a node of application of an initialization potential. For each two successive pixels among the N pixels, the initialization transistor of one of the pixels that is the most distant from the end is connected between the sense nodes of the two pixels.

公开(公告)号：US12004432B2

公开(公告)日：2024-06-04

申请号：US17507645

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Roberto Simola ,  Yohann Moustapha-Rabault

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/231 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/882 ,  H10N70/883

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US20240178053A1

公开(公告)日：2024-05-30

申请号：US18514770

申请日：2023-11-20

Applicant: STMicroelectronics France ,  STMicroelectronics (Crolles 2) SAS

Inventor： Houssein El Dirani ,  Marouane Mastari ,  Mohamed Ali Nsibi

IPC: H01L21/762 ,  H01L23/522

CPC classification number: H01L21/76224 ,  H01L23/5226 ,  H01L23/5227

Abstract: The integrated circuit includes a semiconductor substrate having a front face including isolation structures that extend vertically into the substrate from the front face as far as a first depth, and an interconnection part comprising metal levels incorporating at least one passive component, above the front face of the substrate. The integrated circuit further includes a dielectric structure that is vertically aligned with the position of the at least one passive component, and that extends vertically into the substrate from the front face as far as a second depth that is greater than the first depth.