公开(公告)号：US10522225B1

公开(公告)日：2019-12-31

申请号：US14874366

申请日：2015-10-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L23/528 ,  G11C14/00 ,  H01L27/108 ,  H01L27/11568

Abstract: A semiconductor device, the device including: a plurality of non-volatile memory cells, where at least one of the non-volatile memory cells includes at least one channel facet, where the at least one channel facet is modified by at least two gates, where the at least one channel facet includes at least two storage locations oriented perpendicular to the at least two gates.

公开(公告)号：US10515981B2

公开(公告)日：2019-12-24

申请号：US15761426

申请日：2016-09-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11507 ,  H01L27/118 ,  H01L29/788 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/28

Abstract: A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

公开(公告)号：US20190363179A1

公开(公告)日：2019-11-28

申请号：US16536606

申请日：2019-08-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/66 ,  H01L27/088 ,  H01L23/48 ,  H01L23/34 ,  H01L23/50 ,  H01L27/06 ,  H01L27/02 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L23/544 ,  H01L21/74 ,  H01L29/10 ,  H01L29/808 ,  H01L29/732 ,  H01L27/118 ,  H01L27/11578

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

公开(公告)号：US20190273069A1

公开(公告)日：2019-09-05

申请号：US16409840

申请日：2019-05-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/088 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L21/74

Abstract: A 3D semiconductor device, the device including: a first single crystal layer; at least one first metal layer above the first single crystal layer; a second metal layer above the first metal layer; a plurality of first transistors atop the second metal layer; a plurality of second transistors atop the second transistors; a plurality of third transistors atop the second transistors; a third metal layer above the plurality of third transistors: a fourth metal layer above the third metal layer; and a second single crystal layer above the fourth metal layer; and a plurality of connecting metal paths from the fourth metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the fourth metal layer is providing global power distribution to the device.

公开(公告)号：US20190244933A1

公开(公告)日：2019-08-08

申请号：US16337665

申请日：2017-09-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00

CPC classification number: H01L25/0657 ,  G11C16/10 ,  G11C16/14 ,  H01L21/6835 ,  H01L21/8221 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11597 ,  H01L2221/68363 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596

Abstract: A 3D device, the device including: a first stratum of first bit-cell memory arrays; a second stratum of second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the third stratum overlays the second stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.

公开(公告)号：US10354995B2

公开(公告)日：2019-07-16

申请号：US15922913

申请日：2018-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L29/45 ,  G06F9/00 ,  B82Y10/00 ,  H01L21/84 ,  H01L23/00 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L27/24 ,  H01L29/06 ,  H01L29/66 ,  H01L21/268 ,  H01L21/762 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/786 ,  H01L29/423 ,  H01L27/088 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/112 ,  H01L27/108 ,  H01L27/105 ,  H01L23/544 ,  G03F9/00 ,  H01L27/1157 ,  H01L29/775 ,  H01L21/8234

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.

公开(公告)号：US10297599B2

公开(公告)日：2019-05-21

申请号：US15911071

申请日：2018-03-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11568 ,  H01L27/115 ,  H01L27/108 ,  G11C16/04 ,  H01L27/11578 ,  G11C16/10 ,  H01L27/11573 ,  H01L29/78 ,  H01L29/792

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

公开(公告)号：US20190057959A1

公开(公告)日：2019-02-21

申请号：US16166112

申请日：2018-10-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/18 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a plurality of metal layers; a thermal isolation layer overlaying the first level; a second level of memory circuits, the memory circuits include an array of memory cells, where the second level is overlaying the thermal isolation layer; and connections from the logic circuits to the memory array including vias, where the vias have a diameter of less than 400 nm, and where a majority of the thermal isolation layer includes a material with a less than 0.5 W/m·K thermal conductivity.

公开(公告)号：US20190019693A1

公开(公告)日：2019-01-17

申请号：US16115519

申请日：2018-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/34 ,  H01L23/498 ,  H01L27/098 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

公开(公告)号：US20190006192A1

公开(公告)日：2019-01-03

申请号：US16114211

申请日：2018-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/34 ,  H01L23/498 ,  H01L27/098 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L27/092 ,  H01L23/60 ,  H01L23/522

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.