Patent search ap:("Monolithic 3D Inc.") AND inv:"Israel Beinglass" Page 1

1.

发明授权
3D semiconductor device having two layers of transistors 有权

公开(公告)号：US09613844B2

公开(公告)日：2017-04-04

申请号：US14821683

申请日：2015-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar , Zeev Wurman , Israel Beinglass

IPC: H01L25/065 , H01L23/48 , H01L21/762 , H01L29/78 , H01L27/105 , H01L21/683 , H01L23/544 , H01L27/088 , G11C8/16 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/525 , H01L29/423 , H01L29/66 , H01L21/74 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792 , H01L27/11 , H01L27/112 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/118 , H01L27/12 , H01L23/367 , H01L23/00 , H01L25/00

CPC classification number: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/3677 , H01L23/481 , H01L23/5252 , H01L23/544 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0207 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/10802 , H01L27/10873 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L27/1214 , H01L27/1266 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2225/06558 , H01L2924/00011 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/014 , H01L2924/00015 , H01L2924/00 , H01L2224/80001

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.

2.

发明申请
NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE 有权
Title translation: 新型3D半导体器件和结构

公开(公告)号：US20150348945A1

公开(公告)日：2015-12-03

申请号：US14821683

申请日：2015-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar , Zeev Wurman , Israel Beinglass

IPC: H01L25/065 , H01L23/532 , H01L29/45 , H01L27/088 , H01L27/06 , H01L23/544 , H01L23/522

CPC classification number: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/3677 , H01L23/481 , H01L23/5252 , H01L23/544 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0207 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/10802 , H01L27/10873 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L27/1214 , H01L27/1266 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2225/06558 , H01L2924/00011 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/014 , H01L2924/00015 , H01L2924/00 , H01L2224/80001

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 互连第一晶体管并覆盖第一层的第一互连层; 以及包括第二晶体管的第二层，其中所述第二层厚度小于2微米且大于5nm，其中所述第二层覆盖所述第一互连层，并且其中所述第二层包括通过蚀刻步骤形成的管芯线。

3.

发明申请
3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE 审中-公开

公开(公告)号：US20170186770A1

公开(公告)日：2017-06-29

申请号：US15460230

申请日：2017-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar , Zeev Wurman , Israel Beinglass

IPC: H01L27/11582 , H01L29/16 , H01L27/11575 , H01L29/04 , H01L27/11573 , H01L27/24

CPC classification number: H01L27/11582 , B82Y10/00 , H01L21/6835 , H01L21/76254 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/3677 , H01L23/5252 , H01L23/544 , H01L24/00 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0207 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/10802 , H01L27/10873 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L27/1214 , H01L27/1266 , H01L27/2436 , H01L27/249 , H01L28/00 , H01L29/04 , H01L29/0673 , H01L29/66272 , H01L29/66439 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/775 , H01L29/7841 , H01L29/785 , H01L29/7881 , H01L29/792 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2221/68368 , H01L2223/54426 , H01L2223/54453 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2225/06558 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/014 , H01L2924/00015 , H01L2924/00 , H01L2224/80001 , H01L2224/05599

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

4.

发明申请
SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE 有权

公开(公告)号：US20170133432A1

公开(公告)日：2017-05-11

申请号：US15409740

申请日：2017-01-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Zeev Wurman

IPC: H01L27/24 , H01L29/66 , H01L29/167 , H01L29/78 , H01L45/00 , H01L29/04

CPC classification number: H01L27/2436 , G11C13/0021 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/2236 , H01L21/31116 , H01L21/324 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/544 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L27/249 , H01L29/04 , H01L29/167 , H01L29/66568 , H01L29/78 , H01L29/78696 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/1616 , H01L2223/54426 , H01L2223/54453 , H01L2924/00011 , H01L2224/80001

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

5.

发明申请
SEMICONDUCTOR DEVICE AND STRUCTURE 有权
Title translation: 半导体器件和结构

公开(公告)号：US20160343774A1

公开(公告)日：2016-11-24

申请号：US15224929

申请日：2016-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Zeev Wurman

IPC: H01L27/24 , H01L45/00

CPC classification number: H01L27/2436 , G03F9/7076 , G03F9/7084 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/544 , H01L27/0207 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2223/54426 , H01L2223/54453 , H01L2924/00011 , H01L2224/80001

Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一存储单元; 第二存储单元，包括第二晶体管，其中所述第二晶体管覆盖所述第一晶体管，所述第二晶体管与所述第一晶体管自对准; 以及多个无连接晶体管，其中至少一个无连接晶体管控制对至少一个存储单元的访问。

6.

发明申请
NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE 有权
Title translation: 新型3D半导体器件和结构

公开(公告)号：US20150061036A1

公开(公告)日：2015-03-05

申请号：US14509288

申请日：2014-10-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong

IPC: H01L27/088 , H01L23/48 , H01L23/00 , H01L23/528 , H01L23/532 , H01L27/06 , H01L23/544

CPC classification number: H01L27/088 , G11C17/14 , H01L21/76254 , H01L21/8221 , H01L21/8226 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/544 , H01L24/14 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/0688 , H01L27/0694 , H01L27/092 , H01L27/105 , H01L27/10873 , H01L27/10876 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11803 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H03K17/687 , H03K19/0948 , H03K19/177 , H01L2924/00 , H01L2224/80001 , H01L2224/05599 , H01L2924/00012

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum.

Abstract translation: 一种半导体器件，包括：第一层，包括单晶材料和第一晶体管，所述第一晶体管由第一隔离层覆盖; 包括第二晶体管并覆盖第一隔离层的第二层，第二晶体管包括单晶材料; 至少一个接触到所述第二晶体管，其中所述至少一个触点具有小于200nm的直径; 第一层的第一组外部连接，用于将设备连接到外部设备; 第二组外部连接，覆盖第二层以将设备连接到外部设备; 以及位于第一层和第二层之间的互连层，其中互连层包括铜或铝。

7.

发明授权
3D semiconductor device and structure 有权
Title translation: 3D半导体器件及结构

公开(公告)号：US09564432B2

公开(公告)日：2017-02-07

申请号：US14509288

申请日：2014-10-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong

IPC: H01L27/088 , G11C17/14 , H01L21/762 , H01L21/822 , H01L21/84 , H01L23/525 , H01L23/544 , H01L25/065 , H01L25/18 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/112 , H01L27/118 , H03K17/687 , H03K19/0948 , H03K19/177 , H01L21/8226 , H01L23/48 , H01L23/528 , H01L23/532 , H01L23/00

CPC classification number: H01L27/088 , G11C17/14 , H01L21/76254 , H01L21/8221 , H01L21/8226 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/544 , H01L24/14 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/0688 , H01L27/0694 , H01L27/092 , H01L27/105 , H01L27/10873 , H01L27/10876 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11803 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H03K17/687 , H03K19/0948 , H03K19/177 , H01L2924/00 , H01L2224/80001 , H01L2224/05599 , H01L2924/00012

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; where the second layer includes at least one through layer via to provide connection between at least one of the second transistors and at least one of the first transistors, where the at least one through layer via has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.

Abstract translation: 一种半导体器件，包括：第一层，包括单晶材料和第一晶体管，所述第一晶体管由第一隔离层覆盖; 包括第二晶体管并覆盖第一隔离层的第二层，第二晶体管包括单晶材料; 其中所述第二层包括至少一个贯通层通孔，以在所述第二晶体管中的至少一个与所述第一晶体管中的至少一个之间提供连接，其中所述至少一个贯通层通孔的直径小于200nm; 第一层的第一组外部连接，用于将设备连接到外部设备; 以及覆盖第二层以将设备连接到外部设备的第二组外部连接。

8.

发明授权
Semiconductor memory device and structure 有权

公开(公告)号：US10354995B2

公开(公告)日：2019-07-16

申请号：US15922913

申请日：2018-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Zeev Wurman

IPC: H01L29/45 , G06F9/00 , B82Y10/00 , H01L21/84 , H01L23/00 , H01L23/48 , H01L27/02 , H01L27/06 , H01L27/11 , H01L27/12 , H01L27/24 , H01L29/06 , H01L29/66 , H01L21/268 , H01L21/762 , H01L21/822 , H01L23/367 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/786 , H01L29/423 , H01L27/088 , H01L27/118 , H01L27/11578 , H01L27/11551 , H01L27/112 , H01L27/108 , H01L27/105 , H01L23/544 , G03F9/00 , H01L27/1157 , H01L29/775 , H01L21/8234

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.