公开(公告)号：US6119198A

公开(公告)日：2000-09-12

申请号：US889251

申请日：1997-07-08

申请人： Eric C. Fromm

发明人： Eric C. Fromm

IPC分类号： G06F7/76 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F12/04 ,  G06F5/01

CPC分类号： G06F15/8007 ,  G06F12/0692 ,  G06F15/17381 ,  G06F7/762

摘要： A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in a multidimensional array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a mask word determined from the distribution specification associated with the array. The mask word is generated from the distribution specification and applied to a linearized index associated with a particular array element to obtain processing element number bits and local offset bits. The processing element number bits and local offset bits are then accumulated to create the processing element number and local offset for the memory location associated with the array element.

摘要翻译： 通过递归离心提取PE数和从数组索引偏移的方法。 根据本发明的一个方面，处理单元编号被分配给每个处理单元，将局部存储器地址分配给每个存储器单元，并且线性化索引被分配给多维阵列中的每个阵列元素。 作为与阵列元素相关联的线性化索引和从与阵列相关联的分布规范确定的掩码字的函数来计算其中存储特定数组元素的处理元件的处理元件号。 掩模字从分布规范生成并应用于与特定数组元素相关联的线性化索引，以获得处理元素数位和局部偏移位。 然后累积处理元件数位和局部偏移位以产生与数组元素相关联的存储器位置的处理元件号和本地偏移。

公开(公告)号：US6092226A

公开(公告)日：2000-07-18

申请号：US21651

申请日：1998-02-10

申请人： Allen Kramer ,  Roger Brown ,  Eric Fischer

发明人： Allen Kramer ,  Roger Brown ,  Eric Fischer

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318541

摘要： An input cell to the core logic on an electrical component and an output cell from the core logic on an electrical component are provided with a first signal path for data, a second signal path for scan data, a flip flop positioned near the pad of the core logic for selecting between said first signal path for data and second signal path for scan data. The scan data is used to input special signals or vectors to the core logic and to read the results of the scan data after it has passed through the core data and has been manipulated thereby. Several of the electrical components can be electrically connected to one another. The output cell of a first chip is electrically attached to the input cell of a second electrical component. The individual electrical components are connected on a printed circuit board and typically there are electrical conductors associated with the printed circuit board that are used to electrically connect the first chip or electrical component and the second chip or electrical component.

摘要翻译： 电气元件上的核心逻辑的输入单元和来自电气元件上的核心逻辑的输出单元被提供有用于数据的第一信号路径，用于扫描数据的第二信号路径，位于 用于在用于数据的所述第一信号路径和用于扫描数据的第二信号路径之间进行选择的核心逻辑。 扫描数据用于向核心逻辑输入特殊信号或向量，并在扫描数据通过核心数据后读取扫描数据的结果，并由此进行操作。 几个电气部件可以彼此电连接。 第一芯片的输出单元电连接到第二电气部件的输入单元。 各个电气部件连接在印刷电路板上，并且通常存在与印刷电路板相关联的用于电连接第一芯片或电气部件以及第二芯片或电气部件的电导体。

公开(公告)号：US6085303A

公开(公告)日：2000-07-04

申请号：US972010

申请日：1997-11-17

申请人： Greg Thorson ,  Randal S. Passint ,  Steven L. Scott

发明人： Greg Thorson ,  Randal S. Passint ,  Steven L. Scott

IPC分类号： G06F9/46 ,  G06F15/16

CPC分类号： G06F9/52

摘要： Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping synchronization partitions are available simultaneously through the use of a plurality of parallel synchronization contexts. The present synchronization mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes. The present barrier/eureka mechanism also supports zero to N processor entities at each router node ("leaves" on the barrier tree), and provides a barrier sequence counter for each barrier context in order to resolve potential race conflicts that might otherwise arise.

摘要翻译： 改进的方法和装置，用于在大规模并行处理系统中促进障碍和尤里卡同步。 当前的屏障/尤里卡同步机制提供了一种可分割的，低延迟的，立即可重用的鲁棒机制，其可以在物理数据通信网络上操作，并且可以用于警告所有PE中的所有处理器实体（PE） 在该分区已经到达其个别程序代码中的指定障碍点，或者当该分区中的任何一个PE在其各个程序代码中已经达到指定的尤里卡点时，或者当满足屏障或尤里卡要求时，哪个 曾经来过 多个重叠的同步分区可以通过使用多个并行同步上下文同时获得。 本同步机制可以在专用屏障网络上实现，或者叠加在用于数据交换，操作系统功能和其他目的的物理数据通信网络上操作的虚拟屏障/尤里卡网络。 当前的屏障/尤里卡机制还支持每个路由器节点处的零到N个处理器实体（“阻挡树”上的“离开”），并且为每个屏障上下文提供屏障序列计数器，以便解决否则可能出现的潜在的竞争冲突。

公开(公告)号：US5940625A

公开(公告)日：1999-08-17

申请号：US706808

申请日：1996-09-03

申请人： James E. Smith

发明人： James E. Smith

IPC分类号： G06F9/302 ,  G06F9/312 ,  G06F9/38 ,  G06F15/78 ,  G06F15/00

CPC分类号： G06F9/3001 ,  G06F15/8084 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3836

摘要： A vector processing system which uses vector masks to determine whether or not to perform operations on operands corresponding to bit positions within the mask is disclosed. An approximation of the number of no-operation representative bits in a vector mask register is made, and such bits are skipped to improve the performance of vector mask based operations. The number of consecutive no-op representative bits, as represented by zero values, skipped is a power of two to simplify the circuitry and logic involved in skipping such operations.

摘要翻译： 公开了一种矢量处理系统，其使用矢量掩模来确定是否对与掩模内的位位置相对应的操作数执行操作。 进行矢量屏蔽寄存器中的非操作代表位的数量的近似，并且跳过这些位以提高基于矢量掩码的操作的性能。 跳过由零值表示的连续的无操作代表位的数量是两个功率，以简化跳过这种操作所涉及的电路和逻辑。

公开(公告)号：US5913069A

公开(公告)日：1999-06-15

申请号：US987948

申请日：1997-12-10

申请人： Rabin A. Sugumar ,  Stefanos Kaxiras

发明人： Rabin A. Sugumar ,  Stefanos Kaxiras

IPC分类号： G06F15/78 ,  G06F15/80 ,  G06F15/76

CPC分类号： G06F15/8092 ,  G06F15/8076 ,  G06F15/8084

摘要： A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form an architectural vector register, which are references by vector applications. Memories from nodes together form an aggregate memory. The vector applications load memory vector elements from the memories to the physical vector registers, and store physical vector elements from the physical vector registers to the memories. The memory vector elements are interleaved among the memories of the nodes to reduce inter-node traffic during the loads and the stores.

摘要翻译： 矢量/标量计算机系统具有通过互连网络互连的节点。 每个节点包括向量执行单元，标量执行单元，物理向量寄存器和存储器。 来自节点的物理矢量寄存器一起形成一个架构向量寄存器，它是矢量应用的参考。 来自节点的记忆一起形成聚合记忆。 矢量应用将存储器矢量元素从存储器加载到物理矢量寄存器，并将物理矢量元素从物理矢量寄存器存储到存储器。 存储器矢量元素在节点的存储器之间进行交织，以减少负载和存储期间的节点间流量。

公开(公告)号：US5862313A

公开(公告)日：1999-01-19

申请号：US650632

申请日：1996-05-20

申请人： Timothy J. Johnson ,  Alan R. Rivers

发明人： Timothy J. Johnson ,  Alan R. Rivers

IPC分类号： G06F3/06 ,  G06F11/10 ,  G06F13/00 ,  G06F11/00

CPC分类号： G06F11/1076 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0689

摘要： A system and method for implementing a serial RAID system. Data is striped for the array of disk drives and parity for the striped data is calculated and the resulting data and is written serially to a RAID system over a Fibre Channel or other type of network. The system also allows reading of the striped data and parity serially from the disk array.

摘要翻译： 一种用于实现串行RAID系统的系统和方法。 磁盘驱动器阵列的数据被分割，并且计算条带数据的奇偶校验，并将结果数据通过光纤通道或其他类型的网络串行写入RAID系统。 该系统还允许从磁盘阵列串行读取条带数据和奇偶校验。

公开(公告)号：US5802341A

公开(公告)日：1998-09-01

申请号：US166451

申请日：1993-12-13

申请人： J. Bradley Kline ,  David Wagner ,  Ahmed K. Ezzat

发明人： J. Bradley Kline ,  David Wagner ,  Ahmed K. Ezzat

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/657

摘要： A system and method for virtual memory management. A plurality of virtual memory pages having selectable page sizes are used to tailor memory allocations in a way which balances overallocation of memory against the number of entries saved in accessing that memory through the translation buffer. A library routine can act on the overallocated memory to hide memory requests from the operating system.

摘要翻译： 一种用于虚拟内存管理的系统和方法。 具有可选页面大小的多个虚拟存储器页面被用于以存储器的过度分配与通过翻译缓冲器访问该存储器所保存的条目数量平衡的方式来定制存储器分配。 库程序可以作用于超分配的内存来隐藏来自操作系统的内存请求。

公开(公告)号：US5801924A

公开(公告)日：1998-09-01

申请号：US604888

申请日：1996-02-22

申请人： Richard B. Salmonson

发明人： Richard B. Salmonson

IPC分类号： H05K1/02 ,  H05K1/14 ,  H05K7/20

CPC分类号： H05K7/20254 ,  H05K1/144 ,  H05K7/20509 ,  H05K1/0201 ,  Y10T29/53174

摘要： A method and apparatus for conductively cooling daughter card assemblies mounted to either an air or liquid cooled computer circuit module wherein the module has a cold plate and at least one mother board adjacent the cold plate. The module carries a number of daughter assemblies thereon adjacent the mother board. Each daughter card assembly has at least one daughter board which carries a number of electronic components on an element side of the board. A cooling side is disposed opposite the element side on the board. A thermally conductive plate has an inner side facing the mother board and an outer side opposite the inner side. The inner side has one or more projecting members extending perpendicularly towards the mother board. The daughter board is parallel to and in conductive contact with one side of the conductive plate. The module cold plate has a number of upstanding spacers projecting toward the mother board. A portion of the top of each spacer is exposed for receiving thereon one of the projecting members of the conductive plate in intimate conductive contact. Preferably, the conductive plate is sandwiched between the cooling sides of a pair of daughter boards. Heat generated by the electronic components on the daughter boards is transferred by conduction through the boards into the conductive plate. The heat conducts through the projecting members into the spacers and into the module cold plate. The heat is then carried away by the cooling medium flowing through the cold plate.

摘要翻译： 一种用于导电地冷却安装到空气或液体冷却的计算机电路模块的子卡组件的方法和装置，其中模块具有冷板和邻近冷板的至少一个母板。 该模块在其上邻近母板携带多个子组件。 每个子卡组件具有至少一个子板，其在板的元件侧上承载许多电子部件。 冷却侧与板上的元件侧相对设置。 导热板具有面向母板的内侧和与内侧相对的外侧。 内侧具有垂直于母板延伸的一个或多个突出部件。 子板与导电板的一侧平行并与其导电接触。 模块冷板具有朝向母板突出的多个直立的间隔件。 每个间隔件的顶部的一部分被暴露以在其中接收导电板的突出构件中的一个以紧密的导电接触。 优选地，导电板夹在一对子板的冷却侧之间。 由子板上的电子部件产生的热量通过导电板传导到导电板中。 热量通过突出部件进入隔板并进入模块冷板。 热量然后被流经冷板的冷却介质带走。

公开(公告)号：US5726857A

公开(公告)日：1998-03-10

申请号：US605356

申请日：1996-02-22

申请人： Richard B. Salmonson ,  Stephen A. Bowen

发明人： Richard B. Salmonson ,  Stephen A. Bowen

IPC分类号： H01R12/04 ,  H05K7/20

CPC分类号： H05K7/20509

摘要： An apparatus and method for mounting an edge connector assembly within a circuit module. Connector mounting rails are attached to the sides of a printed circuit board and the circuit board is then joined with a cold plate in order to form a circuit module. The mounting rail is an elongate strip of a substantially rigid material for attachment to the circuit board along one of its edges. The strip has an upper planar surface and inner and outer sides. The inner side is for attaching the strip to the edge of the circuit board. The outer side extends beyond the edge of the circuit board and is adapted to carry thereon a female block of the edge connector assembly. The strip also has a plurality of primary mounting openings formed in a predetermined pattern through the outer side of the strip for attaching the circuit board to a circuit module.

摘要翻译： 一种用于将边缘连接器组件安装在电路模块内的装置和方法。 连接器安装导轨连接到印刷电路板的侧面，然后电路板与冷板接合以形成电路模块。 安装导轨是基本上刚性材料的细长条，用于沿其边缘之一附接到电路板。 该带具有上平面表面和内侧和外侧。 内侧用于将带子连接到电路板的边缘。 外侧延伸超过电路板的边缘，并且适于在其上承载边缘连接器组件的阴块。 该条带还具有多个主要安装开口，其通过带的外侧以预定图案形成，用于将电路板连接到电路模块。

公开(公告)号：US5717881A

公开(公告)日：1998-02-10

申请号：US481060

申请日：1995-06-07

申请人： Douglas R. Beard ,  Andrew E. Phelps ,  Michael A. Woodmansee ,  Richard G. Blewett ,  Jeffrey A. Lohman ,  Alexander A. Silbey ,  George A. Spix ,  Frederick J. Simmons ,  Don A. Van Dyke

发明人： Douglas R. Beard ,  Andrew E. Phelps ,  Michael A. Woodmansee ,  Richard G. Blewett ,  Jeffrey A. Lohman ,  Alexander A. Silbey ,  George A. Spix ,  Frederick J. Simmons ,  Don A. Van Dyke

IPC分类号： G06F12/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F15/16 ,  G06F15/173 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F9/30087 ,  G06F11/3632 ,  G06F15/17381 ,  G06F15/8076 ,  G06F15/8092 ,  G06F8/433 ,  G06F8/45 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3846 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885

摘要： An improved high performance hardwired supercomputer data processing apparatus includes instruction means adpated to issue one and two parcel instructions. Instruction fetch means provides an instruction stream of two parcel items in sequence. Instruction decode means is responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction or two one parcel instructions, for issuing each two parcel instruction for execution during the one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during the one clock cycle and the next succeeding clock cycle.

摘要翻译： 改进的高性能硬连线超级计算机数据处理装置包括用于发出一个和两个包裹指令的指令装置。 指令提取装置依次提供两个包裹项目的指令流。 指令解码装置响应于每个两个宗地项目，以在一个时钟周期内确定两个宗地项目是否是单个两个宗地指令或两个一个包裹指令，用于在一个时钟周期内发出每个两个宗地指令以执行，并发出 一个是两个一个包裹指令中的另一个，用于在一个时钟周期和下一个后续时钟周期期间依次执行。