公开(公告)号：US20100162018A1

公开(公告)日：2010-06-24

申请号：US12630668

申请日：2009-12-03

Applicant: Santhosh SUBRAMANIAN ,  Rajeev Kapoor

Inventor： Santhosh SUBRAMANIAN ,  Rajeev Kapoor

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system and a method for optimizing power in an electronic device are described. The system may be used to implement low power techniques to achieve maximum performance with low battery utilization. A processing load level monitor monitors load(s) on processors. Processor frequencies are updated through the driver until the load is close to 100%, which means that the core frequency is changed to the load processor around 100% at the minimum possible frequency.

Abstract translation: 描述了用于优化电子设备中的功率的系统和方法。 该系统可用于实现低功率技术以在电池利用率低的情况下实现最大性能。 处理负载级别监视器监视处理器上的负载。 处理器频率通过驱动器更新，直到负载接近100％，这意味着核心频率以最小可能频率更改为负载处理器100％左右。

公开(公告)号：US20100156543A1

公开(公告)日：2010-06-24

申请号：US12644984

申请日：2009-12-22

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  H03B5/08 ,  H03B5/32 ,  H03B2200/009 ,  H03L7/0995

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance

Abstract translation: 具有以超矩阵结构排列的多个可操作耦合的环形振荡器的振荡器。 可操作耦合的环形振荡器是相同的或不相同的，并且通过公共的逆变器或尾电流晶体管耦合。 由于环形振荡器在超矩阵结构中的布置，环形振荡器被同步并抵抗频率或相位的任何变化，从而保持一致的相位噪声性能

公开(公告)号：US20100115385A1

公开(公告)日：2010-05-06

申请号：US12613399

申请日：2009-11-05

Applicant: NAVEEN BATRA ,  JITENDRA DASANI

Inventor： NAVEEN BATRA ,  JITENDRA DASANI

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0727 ,  G06F11/0772 ,  G11C29/02 ,  G11C29/024 ,  G11C2029/0409

Abstract: An embodiment of the present disclosure relates to detection of data access element selection errors during data access in data storage arrays. An embodiment of the disclosure describes a system including a data storage array comprising a first and a second error identifier. The error identifiers generate an error signal in case multiple data access elements are selected or no data access element is selected, respectively. A system for detection of data-access-element-selection errors further comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers.

Abstract translation: 本公开的实施例涉及在数据存储阵列中的数据访问期间检测数据访问元素选择错误。 本公开的实施例描述了包括包括第一和第二错误标识符的数据存储阵列的系统。 在选择多个数据访问元素或没有选择数据访问元素的情况下，错误标识符生成错误信号。 用于检测数据访问元件选择错误的系统还包括公共误差信号发生器，当由所述错误标识符中的任一个生成错误信号时，该误差信号发生器提供输出。

公开(公告)号：US07710101B2

公开(公告)日：2010-05-04

申请号：US11833779

申请日：2007-08-03

Applicant: Vijayaraghavan Narayanan ,  Balwant Singh

Inventor： Vijayaraghavan Narayanan ,  Balwant Singh

IPC: G06F1/12 ,  G06F1/04

CPC classification number: G01R29/0273 ,  G01R31/31725 ,  G01R31/31726

Abstract: A circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell implementation under test (IUT) includes a condition checking module, a central control module and a duty cycle measurement module. The condition checking module checks an upper threshold voltage and a lower threshold voltage. The central control module controls a plurality of operations for measuring the frequency. The duty cycle measurement module measures the duty cycle and finally all these modules together and calculates maximum operating frequency of the IUT.

Abstract translation: 用于测量最大工作频率的电路及其相应的占空比（IUT）的输入I / O单元实现包括状态检查模块，中央控制模块和占空比测量模块。 条件检查模块检查上阈值电压和较低阈值电压。 中央控制模块控制用于测量频率的多个操作。 占空比测量模块测量占空比，最后测量所有这些模块，并计算IUT的最大工作频率。

公开(公告)号：US20100095339A1

公开(公告)日：2010-04-15

申请号：US12460976

申请日：2009-07-27

Applicant: Ludovic Rattin ,  Subrata Chatterjee ,  Vishal Jain ,  Nitin Khanna

Inventor： Ludovic Rattin ,  Subrata Chatterjee ,  Vishal Jain ,  Nitin Khanna

IPC: H04N7/173

CPC classification number: H04L12/2801 ,  H04L49/00 ,  H04L49/109

Abstract: The present disclosure discloses a digital communication between the between embedded cable modem (eCM) and embedded set-top box (eSTB) via a shared memory. The communication is carried out by packet transfer mechanism as per the protocol without adding any extra header overhead. The communication link is established between the eSTB and eCM mainly in layer 2 and partly in layer 1 according to an implementation of the OSI model. Further, eSTB is used as an eSAFE device coupled to eCM where the eCM and eSTB are considered to be placed on two SoCs with a separate CPU to each SoC (System-On-Chip) with a shared memory (via high speed data bus protocol). DMA (Direct Memory Access) engines are used to accelerate data transfer and to reduce load. DMA of only eCM, SoC is used to minimize hardware resources.

Abstract translation: 本公开公开了通过共享存储器在嵌入式电缆调制解调器（eCM）和嵌入式机顶盒（eSTB）之间的数字通信。 通过根据协议的分组传送机制进行通信，而不增加额外的头部开销。 根据OSI模型的实现，通信链路主要在第2层和第1层之间建立在eSTB和eCM之间。 此外，eSTB被用作耦合到eCM的eSAFE设备，其中eCM和eSTB被认为被放置在具有单独CPU的两个SoC上，每个SoC（片上系统）具有共享存储器（通过高速数据总线协议 ）。 DMA（直接存储器访问）引擎用于加速数据传输和减少负载。 仅使用eCM的DMA，SoC用于最小化硬件资源。

公开(公告)号：US07689643B2

公开(公告)日：2010-03-30

申请号：US11262496

申请日：2005-10-27

Applicant: Tarun Kumar Vashishta ,  Priyanka Agarwal

Inventor： Tarun Kumar Vashishta ,  Priyanka Agarwal

IPC: G06F7/50

CPC classification number: G06F7/5055 ,  G06F7/5057

Abstract: An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.

Abstract translation: 在FPGA上实现的N位常数系数加法器/减法器的区域有效实现，利用具有单输出生成能力的N个LUT。 它包括来自每个LUT的三个输入用于加法/减法，而不需要额外的逻辑来支持算术模式和进位链。 对于支持4输入LUT的FPGA，通过利用LUT的第四个未使用的输入，动态地执行加法和减法的能力进一步增强了概念。 另一个实施例涉及在具有4输入LUT的FPGA上实现的N位常数系数加法器/减法器的延迟优化实现。 实现中的LUT具有单输出生成能力，无需任何进位生成和传播。 该实现使用N + 1个LUT并给出与所使用的路由资源的N / 2成比例的延迟。 然而，通过使用级联链，实现变得更加有效。 延迟优化通过在两个并行链中进行计算来实现。

公开(公告)号：US07671676B2

公开(公告)日：2010-03-02

申请号：US11900928

申请日：2007-09-12

Applicant: Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik

Inventor： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik

IPC: H03F3/45

CPC classification number: H03F3/45659 ,  H03F1/3211 ,  H03F3/45183 ,  H03F2203/45404 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45434 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

Abstract: A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

Abstract translation: 连续时间共模反馈模块能够在宽范围的输入电压下工作。 共模反馈模块包括共模检测器和用于计算和放大第一输入信号和第二输入信号的参考电压和共模电压的差的放大器。 共模反馈模块包括共模分解器和彼此耦合以提供共模反馈电压的控制电压产生模块。 共模反馈模块提供良好的线性度和宽带宽，无需补偿要求。 共模反馈模块还提供偏置电流和共模偏移的小过程角依赖性。

公开(公告)号：US07656987B2

公开(公告)日：2010-02-02

申请号：US11324199

申请日：2005-12-29

Applicant: Puneet Sareen

Inventor： Puneet Sareen

IPC: H04L7/08 ,  H03L7/08 ,  H03H11/16

CPC classification number: H03K5/135 ,  H03K2005/00247

Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.

Abstract translation: 相位发生器包括相移使能和禁止信号发生器，其连接到其第一输入处的配置位并且在其复位输入处连接到复位信号，用于产生控制信号; 对应于所需相移的配置位。 相位发生器包括在其控制输入处连接到相移使能和禁止信号发生器的输出并连接到其复位输入处的复位信号以提供相位产生信号的逻辑信号发生器件; 连接在逻辑信号发生装置的输出端和相移允许和禁止信号发生器的控制输入端之间的反馈元件，用于向相移使能和禁止信号发生器提供受控的时钟信号。

公开(公告)号：US07627705B2

公开(公告)日：2009-12-01

申请号：US11647524

申请日：2006-12-27

Applicant: Munish Agarwal

Inventor： Munish Agarwal

IPC: G06F13/24

CPC classification number: G06F13/26 ,  Y02D10/14

Abstract: An Interrupt Processor is provided in an embedded system to handle interrupts generated in the system. The function of the interrupt processor is to handle interrupts and execute interrupt routines. It performs code execution for interrupts which require immediate response. The other interrupts received by the interrupt processor are arranged in a queue on the basis of their respective priorities. An interrupt signal is then sent to the main processor which processes all the signals in one go. This prevents multiple and frequent switching of the main processor and hence avoids the switching overhead. Since the main processor operates at low frequency, the system consumes less power as compared to conventional systems.

Abstract translation: 在嵌入式系统中提供了中断处理器来处理系统中产生的中断。 中断处理器的功能是处理中断并执行中断程序。 它对要求立即响应的中断执行代码执行。 中断处理器接收的其他中断根据各自的优先级排列在队列中。 然后中断信号被发送到主处理器，该处理器一次性处理所有信号。 这可以防止主处理器的多次频繁切换，从而避免开关开销。 由于主处理器工作在低频率，与常规系统相比，系统的功耗较低。

公开(公告)号：US07617269B2

公开(公告)日：2009-11-10

申请号：US11196797

申请日：2005-08-03

Applicant: Hitanshu Dewan

Inventor： Hitanshu Dewan

IPC: G06F7/50

CPC classification number: G06F7/501

Abstract: An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for a carry-in of one; a second lookup table for generating a first output for the carry out value for a carry-in of one and a second output for the sum value for a carry-in of zero; a first multiplexer is connected to a first input from the first output of the first lookup table and a second input from the first output of the second lookup table; a second multiplexer is connected to a first input from the second output of the first lookup table and a second input from the second output of the second lookup table; thereby, getting two output taps for sum and carry implementation.

Abstract translation: 一种具有两个输出的改进的逻辑实体，用于有效的加法器和其他宏实现，其提供具有减少的面积要求的快速响应，包括第一查找表，用于为进位输入值产生用于进位输出的第一输出和第二输出，用于 一个结转的总和值; 第二查找表，用于为进位值为零的和值产生一个和第二个输出的进位输出值的第一输出; 第一多路复用器连接到来自第一查找表的第一输出的第一输入和来自第二查找表的第一输出的第二输入; 第二多路复用器连接到来自第一查找表的第二输出的第一输入和来自第二查找表的第二输出的第二输入; 从而获得两个输出抽头的总和并执行。