公开(公告)号：US06413824B1

公开(公告)日：2002-07-02

申请号：US09589953

申请日：2000-06-08

Applicant: Amitava Chatterjee ,  Alec J. Morton ,  Mark S. Rodder ,  Taylor R. Efland ,  Chin-Yu Tsai ,  James R. Hellums

Inventor： Amitava Chatterjee ,  Alec J. Morton ,  Mark S. Rodder ,  Taylor R. Efland ,  Chin-Yu Tsai ,  James R. Hellums

IPC: H01L218234

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

Abstract translation: 高性能数字晶体管（140）和模拟晶体管（144）同时形成。 数字晶体管（140）包括用于最佳性能的口袋区域（134）。 这些袋区域（134）从模拟晶体管（144）的至少漏极侧部分地或完全被抑制，以在漏极侧提供平坦的沟道掺杂分布。 平坦沟道掺杂分布提供高的早期电压和更高的增益。 通过使用用于模拟晶体管（144）的HVLDD种植体实现抑制。

公开(公告)号：US06307230B1

公开(公告)日：2001-10-23

申请号：US09416380

申请日：1999-10-12

Applicant: Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

Inventor： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

IPC: H01L2976

CPC classification number: H01L29/66628 ,  H01L21/31111 ,  H01L29/66545

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract translation: 提供一种具有改进的侧壁栅极结构和结构方法的晶体管。 改进的侧壁栅极结构可以包括具有沟道区域（20）的半导体衬底（12）。 栅极绝缘体（36）可以邻近半导体衬底（12）的沟道区域（20）。 栅极（38）可以邻近栅极绝缘体（36）形成。 侧壁绝缘体（28）可以邻近门（38）的一部分形成。 侧壁绝缘体（28）由氮氧化硅材料构成。 外延层（30）可以邻近侧壁绝缘体（28）的一部分并且基本上在沟道区域（20）的外侧邻近半导体衬底（12）形成。 缓冲层（32）可以与侧壁绝缘体（28）的一部分相邻并且与外延层（30）相邻。

公开(公告)号：US06297125B1

公开(公告)日：2001-10-02

申请号：US09233252

申请日：1999-01-19

Applicant: Somnath S. Nag ,  Amitava Chatterjee ,  Girish A. Dixit

Inventor： Somnath S. Nag ,  Amitava Chatterjee ,  Girish A. Dixit

IPC: H01L2176

CPC classification number: H01L21/7682

Abstract: Air-bridges are formed at controlled lateral separations using the extremely high HF etch rate of a gap-fill spin-on-glass such as uncured hydrogen silsequioxane (HSQ) in combination with other dielectrics having a much slower etch rate in HF. The advantages of an air-bridge system with controlled lateral separations include providing an interconnect isolation dielectric which meets all requirements for sub-0.5 micron technologies and providing a device with reduced reliability problems.

Abstract translation: 使用间隙填充旋涂玻璃（例如未固化的氢硅氧烷（HSQ））的非常高的HF蚀刻速率与HF中具有慢得多的蚀刻速率的其它电介质组合，以可控的横向间隔形成空气桥。 具有受控横向分离的空气桥系统的优点包括提供互补隔离电介质，其满足对于0.5微米以下技术的所有要求，并提供具有降低的可靠性问题的装置。

公开(公告)号：US06287920B1

公开(公告)日：2001-09-11

申请号：US09640485

申请日：2000-08-16

Applicant: Amitava Chatterjee ,  Mahalingam Nandakumar

Inventor： Amitava Chatterjee ,  Mahalingam Nandakumar

IPC: H01L218236

CPC classification number: H01L21/823412

Abstract: A method for forming multiple threshold voltage integrated circuit transistors. Angled pocket type implants (80) are performed to form asymmetric regions (90) and (95). The source and drain regions (120, 121, 122, and 123) are connected such that multiple threshold voltage transistors are formed.

Abstract translation: 一种用于形成多个阈值电压集成电路晶体管的方法。 进行倾斜袋型植入物（80）以形成不对称区域（90）和（95）。 源极和漏极区域（120,121,122和123）被连接成使得形成多个阈值电压晶体管。

公开(公告)号：US06232188B1

公开(公告)日：2001-05-15

申请号：US09124854

申请日：1998-07-29

Applicant: Suhail Murtaza ,  Amitava Chatterjee

Inventor： Suhail Murtaza ,  Amitava Chatterjee

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L21/28562 ,  H01L29/66545

Abstract: A method for forming a MOSFET transistor using a disposable gate process which has no need for a chemical mechanical polishing step to expose the disposable gate after deposition of the field dielectric. The field dielectric is deposited non-conformally by HDP-CVD over a disposable gate structure so that the disposable gate remains partially exposed. After deposition, the partially exposed disposable gate may then be removed by selective isotropic etch. In the space left by the removal of the disposable gate, the gate dielectric may be formed and the gate electrode may be deposited. Eliminating the need for exposure of the disposable gate by CMP eliminates the problem of polish rate dependence on gate pattern density.

Abstract translation: 一种使用一次性栅极工艺形成MOSFET晶体管的方法，该方法不需要在沉积场电介质之后进行化学机械抛光步骤来露出一次性栅极。 场致电介质通过HDP-CVD在一次性栅极结构上非保形沉积，使得一次性栅极保持部分暴露。 沉积后，可以通过选择性各向同性蚀刻去除部分暴露的一次性栅极。 在通过去除一次性栅极留下的空间中，可以形成栅极电介质并且可以沉积栅电极。 通过CMP消除对一次性栅极的曝光的需要消除了抛光率对栅极图案密度的依赖性的问题。

公开(公告)号：US6143625A

公开(公告)日：2000-11-07

申请号：US151374

申请日：1998-09-10

Applicant: Ih-Chin Chen ,  Amitava Chatterjee ,  Somnath S. Nag

Inventor： Ih-Chin Chen ,  Amitava Chatterjee ,  Somnath S. Nag

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).

Abstract translation: 隔离沟槽（60）可以包括形成在半导体层（12）中的沟槽（20）。 阻挡层（22）可以沿着沟槽（20）形成。 可以在阻挡层（22）上方形成保护衬垫（50）。 保护性衬垫（50）可以包括化学沉积的氧化物。 绝缘材料（55）的高密度层可以形成在保护衬垫（50）上的沟槽（20）中。

公开(公告)号：US06125021A

公开(公告)日：2000-09-26

申请号：US841752

申请日：1997-04-30

Applicant: Charvaka Duvvury ,  Steven E. Marum ,  Amitava Chatterjee

Inventor： Charvaka Duvvury ,  Steven E. Marum ,  Amitava Chatterjee

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0251 ,  H01L27/0266

Abstract: An integrated circuit (10) with ESD protection is provided. The integrated circuit (10) includes a clamping device (28) connected to an input pad (12) of the integrated circuit and to ground (22). The clamping device (28) limits the peak voltage of an ESD pulse applied to the input pad (12) by conducting it to ground (22). A protection device (16) is connected to an input pad (12) of the integrated circuit (10) and to ground. The protection device (16) discharges the energy of the ESD pulse to ground. The protection device (16) is coordinated with the clamping device (28) such that the clamping device (28) turns on before the protection device (16).

Abstract translation: 提供具有ESD保护的集成电路（10）。 集成电路（10）包括连接到集成电路的输入焊盘（12）并接地（22）的夹持装置（28）。 钳位装置（28）通过将其接地（22）来限制施加到输入焊盘（12）的ESD脉冲的峰值电压。 保护装置（16）连接到集成电路（10）的输入焊盘（12）并接地。 保护装置（16）将ESD脉冲的能量释放到地。 保护装置（16）与夹紧装置（28）协调，使得夹紧装置（28）在保护装置（16）之前打开。

公开(公告)号：US6114186A

公开(公告)日：2000-09-05

申请号：US893653

申请日：1997-07-11

Applicant: Shin-Puu Jeng ,  Kelly J. Taylor ,  Amitava Chatterjee

Inventor： Shin-Puu Jeng ,  Kelly J. Taylor ,  Amitava Chatterjee

IPC: H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/3121 ,  H01L21/3124 ,  H01L21/31612 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/902

Abstract: An improved method is provided for integrating HSQ into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines. A capping layer such as SiO.sub.2 20 is applied to on top of the low-k material. The HSQ is then heated to cure. A thick SiO.sub.2 planarization layer 22 may then be applied and planarized. In other embodiments, the HSQ and SiO.sub.2 process steps can be repeated for multiple layers of HSQ.

Abstract translation: 提供了一种改进的方法，用于将HSQ集成到集成电路结构和过程中，特别是需要多级互连线的那些。 在优选实施例中，互连线14首先被图案化并蚀刻在衬底10上。低k材料例如氢倍半硅氧烷（HSQ）18跨越晶片的表面旋转以填充互连线之间的区域。 将覆盖层如SiO 2 20施加到低k材料的顶部。 然后将HSQ加热固化。 然后可以施加和平坦化厚的SiO 2平坦化层22。 在其他实施例中，可以针对多层HSQ重复HSQ和SiO 2工艺步骤。

公开(公告)号：US5607867A

公开(公告)日：1997-03-04

申请号：US475268

申请日：1995-06-07

Applicant: Ajith Amerasekera ,  Amitava Chatterjee

Inventor： Ajith Amerasekera ,  Amitava Chatterjee

IPC: H01L27/02 ,  H01L21/265

CPC classification number: H01L27/0259

Abstract: An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

Abstract translation: 具有低集电极 - 基极击穿电压的npn晶体管。 第一导电类型的发射极区域（104,106）位于半导体衬底（102）中。 第二导电类型的基极区域（14）位于发射极区域（104,106）内，并且第一导电类型的浅集电极区域（18）位于基极区域（14）内。 浅集电极区域（18）可以掺杂有砷和/或磷，使得浅集电极区域（18）的掺杂剂浓度和深度提供低的集电极 - 基极击穿电压。

公开(公告)号：US08860147B2

公开(公告)日：2014-10-14

申请号：US11944861

申请日：2007-11-26

Applicant: Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

Inventor： Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L27/118

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract translation: 一个实施例涉及包括至少一个半导体器件的集成电路。 集成电路包括与半导体器件的第一端子相关联的第一接触。 第一触点跨越介电层并且将第一端子耦合到在集成电路上水平传送信号的互连线，其中互连线具有第一组成。 集成电路还包括与半导体器件的第二端子相关联的第二触点。 第二接触跨越电介质层并将第二端子耦合到通孔连接到的着陆焊盘，其中着陆焊盘具有不同于第一组成的第二组成。 还公开了其它电路和方法。