公开(公告)号：US20090189163A1

公开(公告)日：2009-07-30

申请号：US12402480

申请日：2009-03-11

Applicant: Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

Inventor： Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

IPC: H01L29/786

CPC classification number: H01L27/124 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/78642

Abstract: A TFT array substrate includes a substrate, a patterned first metallic layer, a patterned stack layer, a patterned dielectric layer, a patterned transparent conductive layer, and a patterned third metallic layer. Elements of each TFT in the TFT array substrate are arranged vertically, so that the TFT array substrate has relatively small fabrication area and is operable with a high conducting current. Further, the storage capacitance can be enhanced by enclosing or sandwiching the second metallic layer with the common lines and the transparent electrodes. In such a way, pixel flashing caused by those coupled signals can be reduced, thus promoting displaying quality thereof.

Abstract translation: TFT阵列基板包括基板，图案化第一金属层，图案化叠层，图案化电介质层，图案化透明导电层和图案化的第三金属层。 TFT阵列基板中的每个TFT的元件被垂直布置，使得TFT阵列基板具有相对较小的制造面积并且可以以高导电电流工作。 此外，可以通过用公共线和透明电极包围或夹持第二金属层来增强存储电容。 以这种方式，可以减少由这些耦合信号引起的像素闪烁，从而提高其显示质量。

公开(公告)号：US07528407B2

公开(公告)日：2009-05-05

申请号：US11674157

申请日：2007-02-13

Applicant: Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

Inventor： Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

IPC: H01L29/04

CPC classification number: H01L27/124 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/78642

Abstract: A TFT array substrate is provided. The TFT array substrate includes a substrate, a patterned first metallic layer, a patterned semiconductor layer, a patterned transparent conductive layer, a patterned dielectric layer, and a patterned second metallic layer. Elements of each TFT of the TFT array substrate are arranged vertically, so that the TFT array substrate has relatively small fabrication area and is operable with a high conducting current. Further, the storage capacitance can be enhanced by enclosing or sandwiching the transparent electrodes with the common lines and the second metallic layer, or alternatively by enclosing or sandwiching the second metallic layer with the common lines and the transparent electrodes.

Abstract translation: 提供TFT阵列基板。 TFT阵列基板包括基板，图案化第一金属层，图案化半导体层，图案化透明导电层，图案化电介质层和图案化的第二金属层。 TFT阵列基板的每个TFT的元件垂直布置，使得TFT阵列基板具有相对较小的制造面积并且可以以高导通电流工作。 此外，通过用公共线和第二金属层包围或夹着透明电极，或者通过用公共线和透明电极包围或夹持第二金属层，可以增强存储电容。

公开(公告)号：USD584316S1

公开(公告)日：2009-01-06

申请号：US29318293

申请日：2008-05-16

Applicant: Hao Yu Sheng ,  Bin Yu ,  Yan Hui Zha

Designer： Hao Yu Sheng ,  Bin Yu ,  Yan Hui Zha

公开(公告)号：US20080281915A1

公开(公告)日：2008-11-13

申请号：US12113203

申请日：2008-04-30

Applicant: Joseph B. Elad ,  Apperson Hunter Johnson ,  Bin Yu ,  Srikanth V. Kallurkar ,  Jonathan Dale

Inventor： Joseph B. Elad ,  Apperson Hunter Johnson ,  Bin Yu ,  Srikanth V. Kallurkar ,  Jonathan Dale

IPC: G06F15/16

CPC classification number: G06Q30/02 ,  G06Q10/10 ,  Y10S707/912

Abstract: The present invention, known as The Collaboration Portal (COPO), relates generally to the field of automated entity, data processing, system control, and data communications, and more specifically to an integrated method, system, and apparatus for providing computer-accessible benefits for communities of users. It provides a framework for provisioning computer-accessible benefits for communities of users, and can efficiently and robustly distribute the processing in behalf of those users over a decentralized network of computers. The field of the invention generally encompasses enabling appropriate and desired communication among communities of users and organizations, and providing information, goods, services, a works, opportunities, and connections among users and organizations.

Abstract translation: 称为协作门户（COPO）的本发明一般涉及自动化实体，数据处理，系统控制和数据通信领域，更具体地涉及用于提供计算机可访问的益处的集成方法，系统和装置 为社区的用户。 它提供了一个为用户社区提供计算机可访问利益的框架，并且可以通过分散的计算机网络来代表这些用户有效且鲁棒地分发处理。 本发明的领域通常包括在用户和组织的社区之间实现适当和期望的通信，以及在用户和组织之间提供信息，商品，服务，作品，机会和连接。

公开(公告)号：US20080227651A1

公开(公告)日：2008-09-18

申请号：US11089436

申请日：2005-03-24

Applicant: Yanxiu Zhou ,  Bin Yu ,  Kalle Levon

Inventor： Yanxiu Zhou ,  Bin Yu ,  Kalle Levon

IPC: C40B30/00 ,  C40B40/06 ,  C40B50/18

CPC classification number: C12Q1/6825 ,  B01J2219/00653 ,  B01J2219/00713 ,  B01J2219/00722 ,  C12Q1/6874 ,  G01N27/48 ,  C12Q2565/607 ,  C12Q2565/501

Abstract: Cyclic voltammetry (CV) may be used with novel sensors for identifying the presence of target sequences complementary to probe sequences. The sensor may include an electrode layer (which is used as a working electrode in a CV system), a conductive polymer layer, and probes immobilized (e.g., via sulfur) on the conductive polymer layer. The conductive polymer layer may be polyaniline, or the like. The probes may be immobilized on the polymer layer using an electro-chemical immobilization technique in the presence of nucleophiles, such as thiol groups for example. The probes may be oligionucleotides. Thus, the sensors may be used for identifying genomic sequence variations and detecting mismatch base pairs, such as single nucleotide polymorphisms (SNPs) for example.

Abstract translation: 循环伏安法（CV）可用于识别存在与探针序列互补的靶序列的新型传感器。 传感器可以包括电极层（其用作CV系统中的工作电极），导电聚合物层和在导电聚合物层上固定（例如通过硫）的探针）。 导电聚合物层可以是聚苯胺等。 探针可以使用电化学固定技术在亲核试剂例如巯基的存在下固定在聚合物层上。 探针可以是寡核苷酸。 因此，传感器可用于鉴定基因组序列变异并检测错配碱基对，例如单核苷酸多态性（SNP）。

公开(公告)号：US07297581B1

公开(公告)日：2007-11-20

申请号：US11130161

申请日：2005-05-17

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L21/338

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract translation: 掺杂包括衬底的半导体器件的散热片的方法包括在衬底上形成多个翅片结构，每个翅片结构包括形成在翅片上的盖。 该方法还包括执行第一倾斜角度注入过程以用n型杂质掺杂第一对多鳍片结构，并执行第二倾斜角度注入工艺以将第二对多鳍片结构与p型杂质掺杂。

公开(公告)号：US20070216840A1

公开(公告)日：2007-09-20

申请号：US11533704

申请日：2006-09-20

Applicant: Chi-Nan Liao ,  Liang-Bin Yu ,  Yuh-Huah Wang

Inventor： Chi-Nan Liao ,  Liang-Bin Yu ,  Yuh-Huah Wang

IPC: G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/1395 ,  G02F1/133512 ,  G02F2001/134381 ,  G02F2201/122

Abstract: A pixel structure of an active device array substrate is provided. The pixel structure includes a scan line and a data line; an active device electrically coupled to the scan line and the data line; a pixel electrode electrically coupled to the active device, wherein the pixel electrode has at least one opening therein; and at least one island electrode disposed inside the opening, wherein the island electrode is electrically coupled to a voltage V, and the pixel electrode is electrically coupled to a driving voltage Vd that is different from the voltage V, such that a transverse electric field is formed between the island electrode and the pixel electrode.

Abstract translation: 提供有源器件阵列衬底的像素结构。 像素结构包括扫描线和数据线; 电耦合到扫描线和数据线的有源器件; 电耦合到所述有源器件的像素电极，其中所述像素电极在其中具有至少一个开口; 以及设置在所述开口内的至少一个岛电极，其中所述岛电极电耦合到电压V，并且所述像素电极电耦合到不同于所述电压V的驱动电压V 使得在岛状电极和像素电极之间形成横向电场。

公开(公告)号：US20070134778A1

公开(公告)日：2007-06-14

申请号：US11590541

申请日：2006-10-31

Applicant: Christoph Benning ,  Sherrie Sanda ,  Bin Yu

Inventor： Christoph Benning ,  Sherrie Sanda ,  Bin Yu

IPC: C12P7/64 ,  C12N5/04 ,  C12N15/82 ,  C12N1/21

CPC classification number: C12P19/42

Abstract: The present invention is directed to compositions and methods related to the synthesis and modification of uridine-5′-diphospho-sulfoquinovose (UDP-SQ). In particular, the methods of the present invention comprise the utilization of recombinant enzymes from Arabidopsis thaliana, UDP-glucose, and a sulfur donor to synthesize UDP-SQ, and the subsequent modification of UDP-SQ to form compounds including, but not limited to, 6-sulfo-α-D-quinovosyl diaclyglycerol (SQDG) and alkyl sulfoquinovoside. The compositions and methods of the invention provide a more simple, rapid means of synthesizing UDP-SQ, and the subsequent modification of UDP-SQ to compounds including, but not limited to, SQDG.

公开(公告)号：US07183223B1

公开(公告)日：2007-02-27

申请号：US10728909

申请日：2003-12-08

Applicant: Cyrus E. Tabery ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Cyrus E. Tabery ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Abstract translation: 提供了用于形成用于半导体器件的触点的方法。 所述方法可以包括在半导体器件上沉积诸如多晶硅，氮化物，氧化物和/或碳材料的各种材料。 所述方法还可以包括形成接触孔并填充接触孔以形成用于半导体器件的接触。

公开(公告)号：US07179692B2

公开(公告)日：2007-02-20

申请号：US10913409

申请日：2004-08-09

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.

Abstract translation: 形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。 该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。