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公开(公告)号：US07935999B2
公开(公告)日：2011-05-03
申请号：US12710082
申请日：2010-02-22
IPC分类号： H01L21/8242
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
摘要翻译： 存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。 至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。 数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。 存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。 字线间距约为1.5F，而数字线间距约为3F。
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公开(公告)号：US20100148249A1
公开(公告)日：2010-06-17
申请号：US12710082
申请日：2010-02-22
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
摘要翻译： 存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。 至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。 数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。 存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。 字线间距约为1.5F，而数字线间距约为3F。
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公开(公告)号：US07557048B2
公开(公告)日：2009-07-07
申请号：US11472950
申请日：2006-06-21
IPC分类号： H01L21/31
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
摘要翻译： 本发明包括形成和/或钝化半导体结构的方法。 在具体方面，半导体衬底的各种氧化物可以通过将衬底的半导体材料暴露于富氘蒸汽来形成。 在其他方面，半导体结构通过在大于或等于350℃的温度下对该结构进行退火而钝化，同时将构造暴露于富氘化环境。
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公开(公告)号：US07387940B2
公开(公告)日：2008-06-17
申请号：US11200286
申请日：2005-08-09
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/1052
摘要： The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.
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45.发明申请公开(公告)号：US20060263964A1
公开(公告)日：2006-11-23
申请号：US11496288
申请日：2006-07-31
申请人： Chandra Mouli , Ceredig Roberts
发明人： Chandra Mouli , Ceredig Roberts
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/26586 , H01L21/28176 , H01L21/28185 , H01L21/28194 , H01L29/512 , H01L29/518 , H01L29/66659
摘要： A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.
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公开(公告)号：US07105881B2
公开(公告)日：2006-09-12
申请号：US10325159
申请日：2002-12-19
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10873 , H01L21/26586 , H01L21/823425 , H01L27/10888 , Y10S257/905
摘要： The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor construction and no comparable halo region is associated with the other of the source/drain regions of the access transistor construction. The invention also encompasses methods of forming DRAM devices.
摘要翻译： 本发明包括DRAM装置。 该器件具有存取晶体管结构，并且存取晶体管结构具有一对源极/漏极区域。 卤素区域与存取晶体管结构的源极/漏极区域中的一个相关联，并且没有可比较的卤素区域与存取晶体管结构的源极/漏极区域中的另一个相关联。 本发明还包括形成DRAM器件的方法。
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公开(公告)号：US07067378B2
公开(公告)日：2006-06-27
申请号：US10914822
申请日：2004-08-09
IPC分类号： H01L21/336
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.
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48.发明授权Method of forming a capacitor structure and DRAM circuitry having a capacitor structure including interior areas spaced apart from one another in a non-overlapping relationship 失效形成电容器结构的方法和具有电容器结构的DRAM电路，该电容器结构包括以非重叠关系彼此间隔开的内部区域公开(公告)号：US06673670B1
公开(公告)日：2004-01-06
申请号：US09653152
申请日：2000-08-31
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L28/91
摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.
摘要翻译： 描述了电容器，DRAM电路及其形成方法。 在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。 第二容器与节点位置连接并且具有限定第二内部区域的开口。 这些区域以不重叠的关系彼此间隔开。 电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。 在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。 轴是不同的并且彼此间隔开。 在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。 材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。 第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。 在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。
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49.发明授权Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry 有权电接触导电插塞的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法公开(公告)号：US06486018B2
公开(公告)日：2002-11-26
申请号：US09791229
申请日：2001-02-22
IPC分类号： H01L218242
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76802 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.
摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。
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公开(公告)号：US06204110B1
公开(公告)日：2001-03-20
申请号：US09434211
申请日：1999-11-04
IPC分类号： H01L218244
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/11 , H01L27/1112 , Y10S257/904 , Y10S438/979
摘要： A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.
摘要翻译： 从半导体材料形成电阻器的半导体处理方法包括：a）提供与电阻器进行电连接的节点; b）在节点外部提供第一电绝缘材料; c）在所述节点外部的所述第一电绝缘材料中提供暴露的垂直侧壁; d）在所述第一材料的外部和所述第一材料垂直侧壁上方提供第二电绝缘材料，所述第一和第二材料可相对于彼此选择性地蚀刻; e）相对于所述第一材料选择性地各向异性地蚀刻所述第二材料，以在所述第一材料垂直侧壁上方形成基本上垂直延伸的侧壁隔离物，并且向外暴露所述邻近所述侧壁间隔物的所述第一材料，所述间隔件具有内表面和外表面; f）相对于第二材料选择性地蚀刻第一材料以向外暴露间隔件外表面的至少一部分; g）在所述暴露的外隔离物表面上并在所述内间隔件表面上提供半导体材料的保形层，所述共形层与所述节点形成电连接; 以及h）将所述保形层图案化成所需的电阻器形状。 公开了SRAM和其它集成电路的集成电路。
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