公开(公告)号：US07564094B2

公开(公告)日：2009-07-21

申请号：US12004985

申请日：2007-12-21

Applicant: Dong-Hyun Kim ,  Chang-Jin Kang

Inventor： Dong-Hyun Kim ,  Chang-Jin Kang

IPC: H01L21/8238

CPC classification number: H01L21/28282

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract translation: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

公开(公告)号：US20080057733A1

公开(公告)日：2008-03-06

申请号：US11847223

申请日：2007-08-29

Applicant: Seung-Pil CHUNG ,  Dong-Chan KIM ,  Chang-Jin KANG ,  Heung-Sik PARK

Inventor： Seung-Pil CHUNG ,  Dong-Chan KIM ,  Chang-Jin KANG ,  Heung-Sik PARK

IPC: H01L21/31

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086

Abstract: Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.

Abstract translation: 公开了制造半导体集成电路器件的方法。 制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层 层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案 层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。 根据本发明的方法比常规方法更简单和便宜。

公开(公告)号：US07282407B1

公开(公告)日：2007-10-16

申请号：US09008525

申请日：1998-06-29

Applicant: Young-woo Park ,  Jun-yong Noh ,  Bon-young Koo ,  Chang-jin Kang ,  Chul Jung ,  Seok-woo Nam

Inventor： Young-woo Park ,  Jun-yong Noh ,  Bon-young Koo ,  Chang-jin Kang ,  Chul Jung ,  Seok-woo Nam

IPC: H01L21/8242

CPC classification number: H01L27/10852 ,  H01L27/10855 ,  H01L27/10885

Abstract: A semiconductor memory device and method of manufacturing a semiconductor memory device that prevents oxidation of the bit lines caused by misalignment which may occur when patterning a storage electrode. An oxidation preventing layer, such as a nitride layer, is formed over the bit lines or in the contact holes to eliminate the diffusion of oxygen into the bit line structure, thereby preventing oxidation of the bit lines.

Abstract translation: 一种半导体存储器件和半导体存储器件的制造方法，该半导体存储器件防止当图案化存储电极时可能发生的由不对准引起的位线的氧化。 在位线或接触孔中形成诸如氮化物层的氧化防止层，以消除氧向位线结构的扩散，从而防止位线的氧化。

公开(公告)号：US20060284277A1

公开(公告)日：2006-12-21

申请号：US11510349

申请日：2006-08-25

Applicant: Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

Inventor： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

IPC: H01L29/00

CPC classification number: H01L27/10885 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10891

Abstract: A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

Abstract translation: 半导体器件包括：绝缘层，其具有由窄开口重叠的宽开口形成的T形槽，至少部分填充窄开口的位线导电层和填充槽的位线封盖层，使得其 顶表面与绝缘层一样高。 隔板形成在宽开口的内壁上。

公开(公告)号：US20050287738A1

公开(公告)日：2005-12-29

申请号：US11159130

申请日：2005-06-23

Applicant: Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

Inventor： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract translation: 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

公开(公告)号：US06875690B2

公开(公告)日：2005-04-05

申请号：US10625027

申请日：2003-07-22

Applicant: Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

Inventor： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

Abstract translation: 提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。 半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。 在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。 第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部 导电层的表面。 第一间隔件包围第一层间绝缘层上的覆盖层的外表面。 第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。 接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与 盖层

公开(公告)号：US20050001252A1

公开(公告)日：2005-01-06

申请号：US10858727

申请日：2004-06-02

Applicant: Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

Inventor： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract translation: 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US06169009A

公开(公告)日：2001-01-02

申请号：US09203337

申请日：1998-12-02

Applicant: Byong-sun Ju ,  Hyoun-woo Kim ,  Chang-jin Kang ,  Joo-tae Moon ,  Byeong-yun Nam

Inventor： Byong-sun Ju ,  Hyoun-woo Kim ,  Chang-jin Kang ,  Joo-tae Moon ,  Byeong-yun Nam

IPC: H01L2120

CPC classification number: C23F4/00 ,  H01L21/32136 ,  H01L28/60

Abstract: A method of etching a platinum group metal film uses a gas mixture containing argon (Ar), oxygen (O2) and halogen gases and a method of forming a lower electrode of a capacitor uses the etching method. The gas mixture contains O2, Ar, and a third component, preferably a halogen, e.g., chlorine (Cl2) or hydrogen bromide (HBr). In the method of forming a lower electrode, a conductive film containing a metal belonging to a platinum (Pt) group is formed on a semiconductor substrate, a hard mask partially exposing the conductive film is then formed on the conductive film. Then, the exposed conductive film is dry-etched using the hard mask as an etching mask and a three-component gas mixture containing argon (Ar) and oxygen (O2), to form a conductive film pattern beneath the hard mask, and the hard mask is then removed.

Abstract translation: 蚀刻铂族金属膜的方法使用包含氩（Ar），氧（O 2）和卤素气体的气体混合物，并且形成电容器的下电极的方法使用蚀刻方法。 气体混合物含有O 2，Ar和第三组分，优选卤素，例如氯（Cl 2）或溴化氢（HBr）。 在形成下电极的方法中，在半导体衬底上形成含有属于铂（Pt）基团的金属的导电膜，然后在导电膜上形成部分地暴露导电膜的硬掩模。 然后，使用硬掩模作为蚀刻掩模和含有氩（Ar）和氧（O 2）的三组分气体混合物来干燥暴露的导电膜，以在硬掩模下形成导电膜图案，并且硬 然后取下面具。

公开(公告)号：US07709389B2

公开(公告)日：2010-05-04

申请号：US11480545

申请日：2006-07-05

Applicant: Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

Inventor： Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

IPC: H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816 ,  H01L21/76897 ,  Y10S438/947

Abstract: A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.

Abstract translation: 公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。 制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

公开(公告)号：US07618899B2

公开(公告)日：2009-11-17

申请号：US11847223

申请日：2007-08-29

Applicant: Seung-Pil Chung ,  Dong-Chan Kim ,  Chang-Jin Kang ,  Heung-Sik Park

Inventor： Seung-Pil Chung ,  Dong-Chan Kim ,  Chang-Jin Kang ,  Heung-Sik Park

IPC: H01L21/31 ,  H01L21/308

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086

Abstract: Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.

Abstract translation: 公开了制造半导体集成电路器件的方法。 制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层 层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案 层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。 根据本发明的方法比常规方法更简单和便宜。