公开(公告)号：US20130020618A1

公开(公告)日：2013-01-24

申请号：US13379347

申请日：2011-08-12

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/50

CPC classification number: H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

Abstract translation: 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US20120267706A1

公开(公告)日：2012-10-25

申请号：US13379373

申请日：2011-04-22

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66606 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional isolation spacer; source/drain regions located in the substrate on opposite sides of the gate stack structure; epitaxially grown metal silicide located on the source/drain regions; characterized in that, the epitaxially grown metal silicide is in direct contact with a channel region controlled by the gate stack structure, thereby eliminating the high resistance region below the conventional isolation spacer. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

Abstract translation: 本发明公开了一种新颖的MOSFET器件及其实现方法，该器件包括：衬底; 栅极堆叠结构，其任一侧消除了常规隔离间隔物; 源极/漏极区域位于栅极堆叠结构的相对侧上的衬底中; 位于源/漏区上的外延生长金属硅化物; 其特征在于，外延生长的金属硅化物与由栅极堆叠结构控制的沟道区域直接接触，从而消除了传统隔离间隔物下面的高电阻区域。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US20120244784A1

公开(公告)日：2012-09-27

申请号：US13142714

申请日：2011-04-11

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC: B24B53/017 ,  B24B1/00

CPC classification number: B24B37/015 ,  B24B37/20 ,  B24B53/017 ,  Y02P80/30

Abstract: A chemical-mechanical polishing tool and a method for preheating the same are disclosed. The chemical-mechanical polishing tool includes: a polishing pad, a deionized water supply channel, a polishing slurry supply channel and a polishing pad conditioner; and the chemical-mechanical polishing tool further includes: a heating apparatus, adapted to heat DI water fed to the DI water supply channel; a temperature sensor, arranged close to the polishing pad to measure a temperature of the polishing pad; and a preheating control system, connected to the temperature sensor, and adapted to control the DI water supply channel to spray the heated DI water to the polishing pad, and when the temperature measured by the temperature sensor is equal to or higher than a predetermined temperature, to close the DI water supply channel, control the polishing slurry supply channel to spray polishing slurry to the polishing pad, and startup the polishing pad conditioner to dress the polishing pad. The invention can reduce the consumption of polishing consumables by the chemical-mechanical polishing tool during preheating, thereby reducing production cost.

Abstract translation: 公开了一种化学机械抛光工具及其预热方法。 化学机械抛光工具包括：抛光垫，去离子水供应通道，抛光浆料供应通道和抛光垫调节剂; 并且所述化学机械抛光工具还包括：加热设备，其适于加热供给到所述DI供水通道的去离子水; 温度传感器，布置在抛光垫附近以测量抛光垫的温度; 以及预热控制系统，其连接到所述温度传感器，并且适于控制所述DI供水通道将所述加热的去离子水喷射到所述抛光垫，并且当所述温度传感器测量的温度等于或高于预定温度 关闭DI供水通道，控制抛光浆料供应通道将抛光浆料抛光到抛光垫上，并启动抛光垫调节剂来修整抛光垫。 本发明可以通过化学机械抛光工具在预热期间减少抛光耗材的消耗，从而降低生产成本。

公开(公告)号：US20120223431A1

公开(公告)日：2012-09-06

申请号：US13142757

申请日：2011-04-11

Applicant: Chao Zhao ,  Dapeng Chen ,  Wen Ou

Inventor： Chao Zhao ,  Dapeng Chen ,  Wen Ou

IPC: H01L23/48 ,  H01L21/762

CPC classification number: H01L21/76898 ,  H01L21/76224 ,  H01L2924/0002

Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

Abstract translation: 提供了一种硅通孔及其形成方法。 该方法包括：提供半导体衬底，所述半导体衬底包括上表面和相对的下表面; 蚀刻半导体衬底的上表面以形成开口; 用导电材料填充开口以形成第一钉; 蚀刻半导体衬底的下表面以形成凹部，使得第一指甲暴露在凹部的底部; 用可蚀刻的导电材料填充凹部，并蚀刻可蚀刻的导电材料以形成第二钉，使得第二钉与第一钉垂直连接; 以及在所述第二钉和所述半导体衬底之间填充间隙以及所述第二钉和相邻的具有介电层的第二钉之间的间隙。 然后，本发明可以提高硅通孔的可靠性并避免空隙。

公开(公告)号：US07610444B2

公开(公告)日：2009-10-27

申请号：US11539350

申请日：2006-10-06

Applicant: Ambalavanar Arulambalam ,  Richard J Byrne ,  Nevin C. Heintze ,  Qian Gao Xu ,  Jun Chao Zhao

Inventor： Ambalavanar Arulambalam ,  Richard J Byrne ,  Nevin C. Heintze ,  Qian Gao Xu ,  Jun Chao Zhao

IPC: G06F5/10

CPC classification number: G11B20/10 ,  G11B2020/10537 ,  G11B2020/10759 ,  G11B2220/2516 ,  H04L69/22 ,  H04L2012/2849

Abstract: A method includes storing first and second sets of parameters in a register. Each set of parameters defines a storage transaction to store data to a computer readable medium or a retrieval transaction to retrieve data from the computer readable medium. The first storage or retrieval transaction is performed according to the first set of parameters. The second set of parameters is retrieved from the register automatically when the first storage or retrieval transaction is completed, without waiting for a further command from a control processor. The second storage or retrieval transaction is performed according to the retrieved second set of parameters. A system for performing the method and a computer readable medium containing pseudocode for generating an application specific integrated circuit that performs the method are provided.

Abstract translation: 一种方法包括将第一和第二组参数存储在寄存器中。 每组参数定义存储事务以将数据存储到计算机可读介质或检索事务以从计算机可读介质检索数据。 根据第一组参数执行第一个存储或检索事务。 当第一个存储或检索事务完成时，自动从寄存器中检索第二组参数，而不用等待来自控制处理器的进一步命令。 根据检索的第二组参数来执行第二存储或检索事务。 提供一种用于执行该方法的系统和包含用于生成执行该方法的专用集成电路的伪代码的计算机可读介质。

公开(公告)号：US07461214B2

公开(公告)日：2008-12-02

申请号：US11273750

申请日：2005-11-15

Applicant: Ambalavanar Arulambalam ,  David E. Clune ,  Yun Peng ,  Qian Gao Xu ,  Jun Chao Zhao

Inventor： Ambalavanar Arulambalam ,  David E. Clune ,  Yun Peng ,  Qian Gao Xu ,  Jun Chao Zhao

IPC: G06F13/16

CPC classification number: G06F13/1605 ,  G06F13/3625

Abstract: In a method of accessing a single port memory, a plurality of read commands are received from a plurality of requestors for memory read access. A respective plurality of parameters corresponding to each of the plurality of read commands is stored in a memory read command queue. The parameters corresponding to one of the read commands are retrieved from the memory read command queue when the single port memory provides the data corresponding to that read command. One or more of the parameters from the memory read command queue are provided while providing the data from the memory.

Abstract translation: 在访问单个端口存储器的方法中，从多个请求器接收多个读取命令用于存储器读取访问。 对应于多个读取命令中的每一个的相应多个参数被存储在存储器读取命令队列中。 当单端口存储器提供与该读取命令对应的数据时，从存储器读取命令队列中检索与其中一个读取命令相对应的参数。 在从存储器提供数据的同时提供来自存储器读取命令队列的一个或多个参数。

公开(公告)号：US07183604B2

公开(公告)日：2007-02-27

申请号：US10459360

申请日：2003-06-10

Applicant: Eduard Cartier ,  Jerry Chen ,  Chao Zhao

Inventor： Eduard Cartier ,  Jerry Chen ,  Chao Zhao

IPC: H01L29/94

CPC classification number: H01L21/28185 ,  C01G27/02 ,  C01P2002/72 ,  C23C16/40 ,  C23C16/405 ,  C23C16/4412 ,  H01B3/10 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/31604 ,  H01L28/40 ,  H01L29/517 ,  H01L29/518 ,  Y10T428/24917 ,  Y10T428/265

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract translation: 公开了包含HfO 2 N 2和第二化合物的介电材料组合物。 组合物的特征在于至少一部分组合物为立方晶相。 此外，公开了包含这种介电材料化合物的基于半导体的器件及其形成方法。

公开(公告)号：US09224589B2

公开(公告)日：2015-12-29

申请号：US13497768

申请日：2011-11-28

Applicant: Guilei Wang ,  Junfeng Li ,  Chao Zhao

Inventor： Guilei Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  H01L21/768 ,  C23C16/44 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/505 ,  C23C16/56

CPC classification number: H01L21/02 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4404 ,  C23C16/505 ,  C23C16/56 ,  H01L21/76837

Abstract: A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

Abstract translation: 公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

公开(公告)号：US20150035087A1

公开(公告)日：2015-02-05

申请号：US14119864

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形 硅。

公开(公告)号：US08946071B2

公开(公告)日：2015-02-03

申请号：US14364950

申请日：2012-03-23

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/823814 ,  H01L21/2255 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.

Abstract translation: 本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域 。 根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。