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    DQS postamble filtering
    41.
    发明授权
    DQS postamble filtering 失效
    DQS后同步码过滤

    公开(公告)号：US07031222B1

    公开(公告)日：2006-04-18

    申请号：US11046007

    申请日：2005-01-28

    申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    IPC分类号： G11C8/00

    CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

    摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

    摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

    Methods and systems for structured ASIC electronic design automation
    43.
    发明申请
    Methods and systems for structured ASIC electronic design automation 审中-公开
    结构化ASIC电子设计自动化的方法和系统

    公开(公告)号：US20050268268A1

    公开(公告)日：2005-12-01

    申请号：US11140915

    申请日：2005-06-01

    申请人： Teng-I Wang ,  Zhong-Qing Shang

    发明人： Teng-I Wang ,  Zhong-Qing Shang

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/64

    摘要： Electronic design automation (“EDA) methods and systems for structured ASICs include accessing or receiving objects representative of source code for a structured ASIC. The objects are flattened to remove hierarchies associated with the source code, such as functional RTL hierarchies. The flattened objects are clustered to accommodate design constraints associated with the structured ASIC. The clustered objects are floorplanned within a design area of the structured ASIC. The objects are then placed within the portions of the design areas assigned to the corresponding clusters. The objects optionally include logic objects and one or more memory objects and/or proprietary objects, wherein the one or more memory objects and/or proprietary objects are placed concurrently with the logic objects.

    摘要翻译： 用于结构化ASIC的电子设计自动化（“EDA”）方法和系统包括访问或接收代表结构化ASIC的源代码的对象。对象被平坦化以去除与源代码相关联的层次结构，例如功能性RTL层次结构。 集群化以适应与结构化ASIC相关联的设计约束，集群对象在结构化ASIC的设计区域内被布局，然后将对象放置在分配给相应集群的设计区域的部分内，可选地包括逻辑对象和 一个或多个存储器对象和/或专有对象，其中一个或多个存储器对象和/或专有对象与逻辑对象同时放置。

    Programmable on-chip differential termination impedance
    45.
    发明授权
    Programmable on-chip differential termination impedance 有权
    可编程片上差分终端阻抗

    公开(公告)号：US06888369B1

    公开(公告)日：2005-05-03

    申请号：US10622314

    申请日：2003-07-17

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/003 ,  H04L25/02

    CPC分类号： H04L25/0278

    摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.

    摘要翻译： 电路和方法用于集成电路上的阻抗终端。 在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。 晶体管耦合在终端电阻网络中。 晶体管为差分IO引脚提供额外的终端阻抗。 晶体管可以单独打开或关闭，以改变阻抗终止。

    Two-step ripple-free multi-phase buck converter and method thereof
    46.
    发明授权
    Two-step ripple-free multi-phase buck converter and method thereof 有权
    两级无波纹多相降压转换器及其方法

    公开(公告)号：US06839252B2

    公开(公告)日：2005-01-04

    申请号：US10442077

    申请日：2003-05-21

    申请人： Liang-Pin Tai ,  Shwu-Liang Hsieh ,  Hung-I Wang ,  Jing-Meng Liu

    发明人： Liang-Pin Tai ,  Shwu-Liang Hsieh ,  Hung-I Wang ,  Jing-Meng Liu

    IPC分类号： H02M3/158 ,  H02M7/00 ,  G05F1/40

    CPC分类号： H02M3/1584 ,  H02M2001/0029

    摘要： A two-step ripple-free multi-phase buck converter and method thereof comprises a first-stage voltage regulator to convert an input voltage to an intermediate voltage and a second-stage voltage regulator with a phase number not less than two to further convert the intermediate voltage to an output voltage by a split phase control, in which the ratio of the intermediate voltage to the output voltage is intended to the phase number such that the steady state output current of the converter approaches to be ripple-free, and hence the drivers and MOSFETs for the second-stage voltage regulator are lower cost, the efficiency of the second-stage voltage regulator is improved, and a higher slew rate current is obtained for transient driving capabilities.

    摘要翻译： 两级无纹波多相降压转换器及其方法包括将输入电压转换为中间电压的第一级电压调节器和相位数不少于2的第二级稳压器，以进一步转换 通过分相控制将中间电压输出到输出电压，其中中间电压与输出电压的比率旨在达到相位数，使得转换器的稳态输出电流接近无波纹，因此 第二级稳压器的驱动器和MOSFET的成本较低，二级稳压器的效率得到提高，瞬态驱动能力可获得更高的转换速率电流。

    On-chip impedance matching circuit
    47.
    发明授权
    On-chip impedance matching circuit 有权
    片内阻抗匹配电路

    公开(公告)号：US06798237B1

    公开(公告)日：2004-09-28

    申请号：US10044365

    申请日：2002-01-11

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278

    摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.

    摘要翻译： 提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。 本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。 本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。 片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。 阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。

    System for constant angular velocity disk recording and method for laser power control thereof
    48.
    发明授权
    System for constant angular velocity disk recording and method for laser power control thereof 有权
    用于恒定角速度盘记录的系统及其激光功率控制方法

    公开(公告)号：US06711107B2

    公开(公告)日：2004-03-23

    申请号：US09919849

    申请日：2001-08-02

    申请人： Chi-Mou Chao ,  Daw-I Wang ,  Tsung Yueh Shih

    发明人： Chi-Mou Chao ,  Daw-I Wang ,  Tsung Yueh Shih

    IPC分类号： G11B700

    CPC分类号： G11B7/126 ,  G11B7/0037 ,  G11B7/0045

    摘要： The system and method is used for CAV (Constant Angular Velocity) control format recording, whereas the existing disk data is recorded under CLV (Constant Linear Velocity) control format recording. When the PUH receives a laser driver signal, it generates a feed signal and a wobble signal. The feed signal is received by the automatic power control; thereafter the automatic power control generates a first control signal used for causing the laser driver to adjust the laser driver signal. After the ATIP decoder receives the wobble signal, the ATIP decoder generates and outputs ATIP decoded data to the CLV value detector. The CLV value detector receives ATIP decoded data and generates a CLV decoded data to the laser power control. The laser power control receives the CLV decoded data and generates a second control signal used for causing the automatic power control to adjust the first control signal.

    摘要翻译： 系统和方法用于CAV（恒角速度）控制格式记录，而现有的磁盘数据记录在CLV（恒定线速度）控制格式记录下。 当PUH接收到激光驱动器信号时，它产生馈送信号和摆动信号。 进给信号由自动功率控制接收; 此后，自动功率控制产生用于使激光驱动器调整激光驱动器信号的第一控制信号。 在ATIP解码器接收到摆动信号之后，ATIP解码器产生并将ATIP解码的数据输出到CLV值检测器。 CLV值检测器接收ATIP解码数据，并产生CLV解码数据给激光功率控制。 激光功率控制接收CLV解码数据，并产生用于使自动功率控制调节第一控制信号的第二控制信号。

    Co-production of hydrogen and methanol from steam reformate
    49.
    发明授权
    Co-production of hydrogen and methanol from steam reformate 失效
    从蒸汽重整产生氢和甲醇

    公开(公告)号：US06706770B2

    公开(公告)日：2004-03-16

    申请号：US10116465

    申请日：2002-04-04

    申请人： Nitin Madhubhai Patel ,  Shoou-I Wang ,  Eugene S. Genkin

    发明人： Nitin Madhubhai Patel ,  Shoou-I Wang ,  Eugene S. Genkin

    IPC分类号： C07C2700

    CPC分类号： C01B3/56 ,  C01B3/48 ,  C01B2203/0233 ,  C01B2203/0283 ,  C01B2203/042 ,  C01B2203/043 ,  C01B2203/0475 ,  C01B2203/061 ,  C01B2203/0827 ,  C01B2203/1241 ,  C01B2203/148 ,  C07C29/1518 ,  C07C31/04

    摘要： Method for the production of methanol and hydrogen which comprises steam reforming a hydrocarbon-containing feed in a steam reforming zone to yield a synthesis gas comprising hydrogen, carbon monoxide, and carbon dioxide; introducing a first portion of the synthesis gas into a methanol synthesis zone to form methanol; reacting a second portion of the synthesis gas with steam to convert carbon monoxide to hydrogen and carbon dioxide to yield a shifted synthesis gas; cooling the shifted synthesis gas to yield a cooled shifted synthesis gas; separating the cooled shifted synthesis gas into a high-purity hydrogen product stream and a reject stream enriched in carbon dioxide; and introducing some or all of the reject stream into either or both of the steam reforming zone and the methanol synthesis zone.

    摘要翻译： 用于生产甲醇和氢的方法，其包括在蒸汽重整区中蒸汽重整含烃进料以产生包含氢气，一氧化碳和二氧化碳的合成气; 将第一部分合成气引入甲醇合成区以形成甲醇; 使第二部分合成气与蒸汽反应，以将一氧化碳转化为氢气和二氧化碳，产生经移动的合成气; 冷却经移动的合成气以产生冷却的转移合成气; 将冷却的转移的合成气分离成富含二氧化碳的高纯度氢产物流和排出物流; 并将一部分或全部废料流引入蒸汽重整区和甲醇合成区中的任一个或两者。

    Apparatus and method for balancing channel currents in a multi-phase DC-to-DC converter
    50.
    发明授权
    Apparatus and method for balancing channel currents in a multi-phase DC-to-DC converter 有权
    用于平衡多相DC-DC转换器中的通道电流的装置和方法

    公开(公告)号：US06414470B1

    公开(公告)日：2002-07-02

    申请号：US10051136

    申请日：2002-01-22

    申请人： Jing-Meng Liu ,  Liang-Pin Tai ,  Hung-I Wang

    发明人： Jing-Meng Liu ,  Liang-Pin Tai ,  Hung-I Wang

    IPC分类号： G05F140

    CPC分类号： H02M3/1584 ,  H02J1/102

    摘要： An apparatus and method for current balance in a multi-phase DC-to-DC converter with a converter output voltage and a plurality of channel currents employs for each channel a multi-input pulse width modulator or an ordinary pulse width modulator in conjunction with a multi-input comparator to produce a respective PWM signal to regulate the corresponding channel current. In addition to the comparison of the converter output voltage with a reference signal to produce an error signal, the apparatus and method compares the error signal with a ramp signal and the corresponding channel current with each of the other channel currents with the multi-input pulse width modulator. Alternatively, a ramp signal is compared by the ordinary pulse width modulator with a signal derived from the multi-input comparator which subtracts the corresponding channel current from each other channel current and sums the error signal.

    摘要翻译： 具有转换器输出电压和多个通道电流的多相DC-DC转换器中的电流平衡的装置和方法为每个通道使用多输入脉宽调制器或普通脉冲宽度调制器 多输入比较器产生相应的PWM信号来调节相应的通道电流。 除了将转换器输出电压与参考信号进行比较以产生误差信号之外，装置和方法还将误差信号与斜波信号和相应的通道电流与多输入脉冲中的每一个通道电流进行比较 宽度调制器 或者，通过普通脉冲宽度调制器将斜坡信号与从多输入比较器导出的信号进行比较，该信号从彼此的通道电流中减去对应的通道电流，并对误差信号求和。