公开(公告)号：US08283248B2

公开(公告)日：2012-10-09

申请号：US13234558

申请日：2011-09-16

Applicant: Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

Inventor： Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

IPC: H01L21/4763

CPC classification number: H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

Abstract translation: 一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层 使得它们之间形成空隙。 该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上 门结构。 所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

公开(公告)号：US20120100706A1

公开(公告)日：2012-04-26

申请号：US13241788

申请日：2011-09-23

Applicant: Jae-hwang Sim ,  Min-chul Kim

Inventor： Jae-hwang Sim ,  Min-chul Kim

IPC: H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548

Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.

Abstract translation: 一些实施例提供了微电子制造方法，其中在衬底上形成牺牲图案。 在衬底上形成间隔物形成层，间隔物形成层覆盖牺牲图案。 蚀刻间隔物形成层以暴露牺牲图案的上表面并且在牺牲图案的至少一个侧壁上留下至少一个间隔物。 消除具有第一宽度的牺牲图案的第一部分，同时保留牺牲图案的第二部分具有大于第一宽度的第二宽度，从而形成包括至少一个间隔物的复合掩模图案，以及部分 牺牲层。 使用复合掩模图案作为蚀刻掩模蚀刻衬底的下面部分。

公开(公告)号：US20120064710A1

公开(公告)日：2012-03-15

申请号：US13230228

申请日：2011-09-12

Applicant: Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

Inventor： Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

IPC: H01L21/28

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract translation: 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

公开(公告)号：US08129238B2

公开(公告)日：2012-03-06

申请号：US12951490

申请日：2010-11-22

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/8242

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US20110165757A1

公开(公告)日：2011-07-07

申请号：US12951490

申请日：2010-11-22

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US20110115093A1

公开(公告)日：2011-05-19

申请号：US12950347

申请日：2010-11-19

Applicant: Yoonmoon PARK ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

Inventor： Yoonmoon PARK ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

IPC: H01L23/528

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿过芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

公开(公告)号：US20110092048A1

公开(公告)日：2011-04-21

申请号：US12795025

申请日：2010-06-07

Applicant: Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

Inventor： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/823481 ,  H01L27/1052

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.

Abstract translation: 形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案 区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物 上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

公开(公告)号：US07842571B2

公开(公告)日：2010-11-30

申请号：US11623269

申请日：2007-01-15

Applicant: Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

Inventor： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

IPC: H01L21/336

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

Abstract: In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.

Abstract translation: 在一个实施例中，半导体器件包括奇数触点和相应的奇数行。 间隔物形成在奇数行的侧壁上，并且通过执行蚀刻工艺形成均匀线的均匀开口。 偶数触点形成在均匀开口中，然后形成均匀的线。

公开(公告)号：US07772069B2

公开(公告)日：2010-08-10

申请号：US12074992

申请日：2008-03-07

Applicant: Sang-Yong Park ,  Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Jae-Kwan Park

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11524 ,  H01L27/11568

Abstract: A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.

Abstract translation: 提供一种形成半导体器件的方法。 多个第一引导图案形成在基板上。 掩模层在基底上共形地形成。 第二引导图案形成在第一引导图案的相应侧上的空白区域中。 掩模层被平坦化，并且去除第一和第二引导图案。 通过各向异性蚀刻工艺蚀刻掩模层。

公开(公告)号：US20090286404A1

公开(公告)日：2009-11-19

申请号：US12453307

申请日：2009-05-06

Applicant: Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-Hwang Sim

Inventor： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-Hwang Sim

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

Abstract translation: 更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案 在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作 第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。