公开(公告)号：US07339834B2

公开(公告)日：2008-03-04

申请号：US11144264

申请日：2005-06-03

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

摘要翻译： 公开了一种用于编程非易失性存储器的系统，其通过将起始编程电压设置为新鲜部件的第一电平并在存储器循环时调整起始编程电压来提高性能。 例如，该系统使用具有第一初始值的增加的程序信号在第一时段期间对一组非易失性存储元件进行编程，并且随后使用增加的程序信号在第二周期期间对该组非易失性存储元件进行编程， 第二初始值，其中第二周期在第一周期之后且第二初始值不同于第一初始值。

公开(公告)号：US20070171744A1

公开(公告)日：2007-07-26

申请号：US11320917

申请日：2005-12-28

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

摘要翻译： 本发明提供了一种用于感测存储器单元的方案。 所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。 存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。 位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值 到达目前，当前基本上关闭。 特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

公开(公告)号：US20070159888A1

公开(公告)日：2007-07-12

申请号：US11332567

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C27/005 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US20070153573A1

公开(公告)日：2007-07-05

申请号：US11681188

申请日：2007-03-02

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

摘要翻译： 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

公开(公告)号：US20070121383A1

公开(公告)日：2007-05-31

申请号：US11624052

申请日：2007-01-17

申请人： Jian Chen ,  Jeffrey Lutze ,  Yan Li ,  Daniel Guterman ,  Tomoharu Tanaka

发明人： Jian Chen ,  Jeffrey Lutze ,  Yan Li ,  Daniel Guterman ,  Tomoharu Tanaka

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

摘要翻译： 通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。 例如，一组编程脉冲被施加到一组闪存单元的字线。 确定哪些存储器单元更容易编程，哪些存储器单元难以编程。 可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。 然后，编程过程将继续调整的位线电压（或其他参数）。

公开(公告)号：US20060160305A1

公开(公告)日：2006-07-20

申请号：US11277907

申请日：2006-03-29

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

摘要翻译： 柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。 每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。 这个过程的很多方面都是自相矛盾的。 这些存储单元的阵列将需要较少的分割。 此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

公开(公告)号：US20060133156A1

公开(公告)日：2006-06-22

申请号：US11316475

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

公开(公告)号：US20060098494A1

公开(公告)日：2006-05-11

申请号：US11316119

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

IPC分类号： G11C16/04

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

公开(公告)号：US20050180186A1

公开(公告)日：2005-08-18

申请号：US10778634

申请日：2004-02-13

申请人： Jeffrey Lutze ,  Nima Mokhlesi

发明人： Jeffrey Lutze ,  Nima Mokhlesi

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/02

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

摘要： A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 每个所述非易失性存储元件包括在衬底中的通道的相对侧处的源极/漏极区域和在沟道上方的浮动栅极堆叠。 存储器系统还包括位于相邻浮动栅极堆叠之间并电连接到源极/漏极区域的一组屏蔽板，用于减少相邻浮动栅极之间的耦合。 屏蔽板选择性地生长在存储器的有效区域上，而不会在非活动区域上生长。 在一个实施例中，屏蔽板是位于源/漏区上方的外延生长的硅。

公开(公告)号：US20050057968A1

公开(公告)日：2005-03-17

申请号：US10665685

申请日：2003-09-17

申请人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

发明人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

IPC分类号： G01R31/28 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

摘要翻译： 本发明提出了用于鉴别具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。