公开(公告)号：US08038864B2

公开(公告)日：2011-10-18

申请号：US11829129

申请日：2007-07-27

Applicant: Koji Arita ,  Ryohei Kitao

Inventor： Koji Arita ,  Ryohei Kitao

IPC: C25D21/12

CPC classification number: C25D21/12 ,  H01L21/2885 ,  H01L21/76877

Abstract: A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr=S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.

Abstract translation: 制造本发明的半导体器件的方法包括：用导电材料填充设置在形成在基板上的绝缘膜的多个凹槽的电镀工艺，其中所述电镀工艺包括执行步骤（S104）的工艺步骤（S104） 以第一电流密度进行电镀，该第一电流密度通过基于第一表面积S1的表面积Sr = S1 / S2在衬底的整个表面上的比率校正预定的第一参考电流密度而得到，该第一电流密度包括 在半导体基板的整个表面上的多个凹部和在不包括多个凹部的侧壁的区域的基板的整个表面上的第二表面区域S2，当不大于预定宽度的细凹槽时， 在所有多个凹部中，填充有导电材料。

公开(公告)号：US07981760B2

公开(公告)日：2011-07-19

申请号：US12669812

申请日：2009-05-07

Applicant: Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

Inventor： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

IPC: H01L21/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

Abstract translation: 一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层 的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

公开(公告)号：US07960770B2

公开(公告)日：2011-06-14

申请号：US12445380

申请日：2007-10-12

Applicant: Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

Inventor： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC: H01L29/76

CPC classification number: H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract translation: 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29），以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US20110002155A1

公开(公告)日：2011-01-06

申请号：US12677413

申请日：2009-05-01

Applicant: Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Takashi Okada

Inventor： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Takashi Okada

IPC: G11C11/00 ,  H01L29/47 ,  H01L21/02

CPC classification number: H01L27/101 ,  H01L27/24 ,  H01L45/00

Abstract: A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises α-tungsten.

Abstract translation: 一种存储元件（3），其以矩阵形式布置在存储器件中，并且包括响应于施加到其上的正或负电脉冲而切换其电阻值的电阻可变元件（1），并保持所述开关电阻值; 以及电流控制元件（2），用于控制当电脉冲施加到电阻可变元件（1）时流动的电流; 其中所述电流控制元件（2）包括第一电极; 第二电极; 以及夹在所述第一电极和所述第二电极之间的电流控制层; 并且其中所述电流控制层包括SiN x，并且所述第一电极和所述第二电极中的至少一个包括α-钨。

公开(公告)号：US20100308298A1

公开(公告)日：2010-12-09

申请号：US12745599

申请日：2009-09-29

Applicant: Takeki Ninomiya ,  Koji Arita ,  Takumi Mikawa ,  Satoru Fujii

Inventor： Takeki Ninomiya ,  Koji Arita ,  Takumi Mikawa ,  Satoru Fujii

IPC: H01L45/00 ,  H01L21/16

CPC classification number: H01L45/1675 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element includes a first electrode (103) formed on a substrate (101), a resistance variable layer (108) and a second electrode (107), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (104), a second transition metal oxide layer (106) which is higher in oxygen concentration than the first transition metal oxide layer (104), and a transition metal oxynitride layer (105). The second transition metal oxide layer (106) is in contact with either one of the first electrode (103) and the second electrode (107). The transition metal oxynitride layer (105) is provided between the first transition metal oxide layer (104) and the second transition metal oxide layer (106).

Abstract translation: 非易失性存储元件包括形成在基板（101）上的第一电极（103），电阻变化层（108）和第二电极（107），其中电阻变化层具有至少三层的多层结构 其是第一过渡金属氧化物层（104），氧浓度高于第一过渡金属氧化物层（104）的第二过渡金属氧化物层（106）和过渡金属氮氧化物层（105）。 第二过渡金属氧化物层（106）与第一电极（103）和第二电极（107）中的任一个接触。 过渡金属氧氮化物层（105）设置在第一过渡金属氧化物层（104）和第二过渡金属氧化物层（106）之间。

公开(公告)号：US20100190313A1

公开(公告)日：2010-07-29

申请号：US12669812

申请日：2009-05-07

Applicant: Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

Inventor： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

IPC: H01L21/8246

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

Abstract translation: 一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层 的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 形成掩模层，形成预定的形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

公开(公告)号：US07229916B2

公开(公告)日：2007-06-12

申请号：US10892352

申请日：2004-07-16

Applicant: Ryohei Kitao ,  Koji Arita

Inventor： Ryohei Kitao ,  Koji Arita

IPC: H01L21/4763

CPC classification number: H01L21/2885 ,  H01L21/76877

Abstract: A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.

Abstract translation: 提供一种制造半导体器件的方法，其提高了通过互连沟槽或通孔中的电解电镀工艺形成的导电层的填充性能，并且实现了自底向上性能的更高的面内均匀性 。 在半导体衬底上的电介质层中形成的互连沟槽和通路孔中的至少一个填充导电层的电解电镀工艺包括：以预定的积分电流密度执行电镀操作的第一步骤，该电镀操作是产品 电流密度，表示包含构成导电层的材料的电镀溶液的每单位面积的电流值和电镀时间，以及在比第一步骤低的电流密度下进行电镀操作的第二步骤。

公开(公告)号：US20070045861A1

公开(公告)日：2007-03-01

申请号：US11591704

申请日：2006-11-02

Applicant: Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

Inventor： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.

Abstract translation: 半导体器件具有半导体衬底和设置在其上的多层布线装置。 多层绞合装置包括其中形成有金属布线图案的至少一个绝缘层结构。 绝缘层结构包括第一SiOCH层，形成在第一SiOCH层上的第二SiOCH层和形成在第二SiOCH层上的二氧化硅（SiO 2）层。 第二SiOCH层的碳（C）密度低于第一SiOCH层的碳（C）密度，氢（H）密度低于第一SiOCH层的密度，氧（O）密度高于第一SiOCH层 。

公开(公告)号：US20050245075A1

公开(公告)日：2005-11-03

申请号：US11174595

申请日：2005-07-06

Applicant: Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

Inventor： Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

IPC: G03F7/40 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L27/15

CPC classification number: H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

Abstract: Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

公开(公告)号：US06927495B2

公开(公告)日：2005-08-09

申请号：US10642279

申请日：2003-08-18

Applicant: Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

Inventor： Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

IPC: G03F7/40 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L27/15 ,  H10L23/48 ,  H10L23/52 ,  H10L29/40

CPC classification number: H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

Abstract: Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

Abstract translation: 公开了具有精密加工的双镶嵌结构的半导体器件。 半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有 沟槽图案。 至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。 光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。 使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。