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公开(公告)号：US09331709B2
公开(公告)日：2016-05-03
申请号：US14162572
申请日：2014-01-23
Applicant: LINEAR TECHNOLOGY CORPORATION
Inventor： Jesper Steensgaard-Madsen
CPC classification number: H03M1/201 , H03M1/0641 , H03M1/0668 , H03M1/462 , H03M1/468
Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.
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公开(公告)号：US09231611B2
公开(公告)日：2016-01-05
申请号：US14162567
申请日：2014-01-23
Applicant: LINEAR TECHNOLOGY CORPORATION
Inventor： Jesper Steensgaard-Madsen
CPC classification number: H03M1/201 , H03M1/0641 , H03M1/0668 , H03M1/462 , H03M1/468
Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.
Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。
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43.发明申请PSE CONTROLLER IN PoE SYSTEM DETECTS DIFFERENT PDs ON DATA PAIRS AND SPARE PAIRS 有权PoE系统中的PSE控制器检测数据对和备用对上的不同PD公开(公告)号：US20150326403A1
公开(公告)日：2015-11-12
申请号：US14705849
申请日：2015-05-06
Applicant: Linear Technology Corporation
Inventor： David Dwelley , Jeffrey Heath , Heath Stewart , Michael Paul
IPC: H04L12/10
CPC classification number: H04L12/10 , G01R31/041 , G06F1/26 , G06F1/266 , H04L49/351
Abstract: A PSE includes a PSE controller that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs, via a switch, if certain conditions are met. Two different levels of currents are supplied to different terminals of the PSE controller that are connected to the data wire pairs and the spare wire pairs, and the resulting voltages are measured. The voltages are used to determine the PD impedances at the ends of the data wire pairs and spare wire pairs to determine whether a PD is connected to the data wire pair, whether another PD is connected to the spare wire pair, or whether a single PD is connected to both the data wire pairs and the spare wire pairs.
Abstract translation: PSE包括一个PSE控制器，它与连接到数据线对和备用线对的任何PD执行握手程序，并且在满足某些条件的情况下通过开关对数据线对和备用线对施加电力。 向连接到数据线对和备用线对的PSE控制器的不同端子提供两个不同电平的电流，并且测量所得到的电压。 电压用于确定数据线对和备用线对端的PD阻抗，以确定PD是否连接到数据线对，无论另一个PD是否连接到备用线对，还是单个PD 连接到数据线对和备用线对。
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公开(公告)号：US09172364B2
公开(公告)日：2015-10-27
申请号：US14157300
申请日：2014-01-16
Applicant: Linear Technology Corporation
Inventor： Gerd Trampitsch
CPC classification number: H03K17/063 , G11C27/02 , H03K3/356034 , H03K17/165 , H03K2217/0009 , H03K2217/0054 , H03M1/124 , H03M1/129
Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.
Abstract translation: 能够在远离正电源轨的输入信号下工作的自举开关电路可以包括（a）具有耦合到输入端的第一端子，耦合到输出端子的第二端子的开关， 和控制终端; （b）电荷泵，其耦合到一个或多个时钟信号，并经由第一电容器和第二电容器与定时电路隔离，所述电荷泵产生输出电压; 以及（c）逻辑电路，其耦合到一个或多个时钟信号，并经由第三电容器和第四电容器与所述定时控制电路隔离，其中所述逻辑电路向所述开关的控制端提供控制信号， 电荷泵的输出电压。
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公开(公告)号：US20150303824A1
公开(公告)日：2015-10-22
申请号：US14531520
申请日：2014-11-03
Applicant: Linear Technology Corporation
Inventor： Jonathan Wayde CELANI
CPC classification number: H02M7/217 , H02J5/005 , H02J17/00 , H02J50/12 , H02M2001/0058 , Y02B70/1441 , Y02B70/1491
Abstract: A control system is provided for controlling a power receiving circuit which is configured for receiving power wirelessly and producing an output voltage. The power receiving circuit has a resonant LC circuit including an inductive element and a capacitive element coupled in parallel. The control system includes a switching circuit coupled in parallel to the resonant LC circuit, and a feedback loop circuit configured for regulating the output voltage by controlling duration during which the switching circuit is in a conductive state in each cycle of a voltage developed across the resonant LC circuit.
Abstract translation: 提供一种用于控制被配置为无线地接收电力并产生输出电压的电力接收电路的控制系统。 电力接收电路具有包括并联耦合的电感元件和电容元件的谐振LC电路。 控制系统包括并联耦合到谐振LC电路的开关电路，以及反馈回路电路，其被配置为通过控制在谐振周期内的每个周期中开关电路处于导通状态的持续时间来调节输出电压 LC电路。
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Patent Agency Ranking
公开(公告)号：US20150295735A1
公开(公告)日：2015-10-15
申请号：US14681529
申请日：2015-04-08
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner
CPC classification number: H04L25/0274 , G06F13/4072 , H02H9/008 , H04L12/10 , H04L12/40045 , H04L25/0266
Abstract: A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and Ethernet data over a single twisted wire pair to a Powered Device (PD). The PSE supplies the DC current and AC data through a cascaded coupling network including a series of AC-blocking inductor stages having different inductances to substantially filter out the AC component and pass the DC component. The data is supplied to the wires via capacitors. The PD may have a matched decoupling network for providing the separated DC power and data to a PD load.
Abstract translation: 数据线上电（PoDL）系统包括通过单个双绞线将DC电源和以太网数据提供给有源设备（PD）的电源设备（PSE）。 PSE通过级联耦合网络提供直流电流和交流数据，包括具有不同电感的一系列交流阻塞电感级，以实质上滤除交流分量并通过直流分量。 数据通过电容器提供给导线。 PD可以具有匹配的去耦网络，用于将分离的DC功率和数据提供给PD负载。
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公开(公告)号：US20150295589A1
公开(公告)日：2015-10-15
申请号：US14669508
申请日：2015-03-26
Applicant: LINEAR TECHNOLOGY CORPORATION
Inventor： Daniel James Eddleman , Chad Thomas Steward
IPC: H03M1/82
Abstract: A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.
Abstract translation: A转换器可以产生代表时间编码信号的模拟输出。 电路可以包括接收时间编码信号的输入端口; 耦合到输入端口的时间编码到数字转换器; 以及耦合到时间编码到数字转换器的数模转换器。
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公开(公告)号：US09152158B2
公开(公告)日：2015-10-06
申请号：US13969893
申请日：2013-08-19
Applicant: Linear Technology Corporation
Inventor： Robert Dobkin , Amitkumar Pravin Patel
Abstract: A linear regulator integrated circuit may be formed having four external terminals including a voltage input (Vin) terminal, a voltage output (Vout) terminal, a Set terminal, and an operational amplifier (op amp) power terminal. A user connects an external resistor to the Set terminal for creating a reference voltage. An op amp controls a pass (or series transistor) to cause an output voltage at the Vout terminal to equal the reference voltage. The op amp has a first power supply terminal internally coupled to the Vin terminal and a second power supply terminal coupled to the op amp power terminal. The op amp power terminal allows a user to externally couple the op amp second power supply terminal to either the Vout pin (for high voltage applications), system ground (for medium voltage applications), or another voltage (to provide additional headroom in very low voltage applications).
Abstract translation: 线性稳压器集成电路可以形成为具有包括电压输入（Vin）端子，电压输出（Vout）端子，设置端子和运算放大器（运算放大器）功率端子）的四个外部端子。 用户将外部电阻连接到设置端子以创建参考电压。 运算放大器控制通过（或串联晶体管），使Vout端子处的输出电压等于参考电压。 运算放大器具有内部耦合到Vin端子的第一电源端子和耦合到运算放大器电源端子的第二电源端子。 运算放大器电源端子允许用户将运算放大器第二电源端子外部耦合到Vout引脚（用于高电压应用），系统地（用于中压应用）或另一电压（以提供更低的额外余量） 电压应用）。
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公开(公告)号：US09077374B2
公开(公告)日：2015-07-07
申请号：US14052479
申请日：2013-10-11
Applicant: Linear Technology Corporation
Inventor： Gerd Trampitsch
CPC classification number: H03M3/472 , H03M1/00 , H03M1/12 , H03M1/1225 , H03M3/30 , H03M3/39 , H03M3/458 , H03M3/464
Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.
Abstract translation: 方法和ADC电路对模拟值使用多个SD调制，并对来自SD调制的脉冲密度调制（PDM）流的数字后处理在给定的过采样比获得更高分辨率的数字输出值中。 SD ADC不会面临每个额外的分辨率的转换时间加倍的约束。 在一个实现中，SD ADC包括在SD相和分辨率提升阶段的转换。 在SD相位期间，使用第一次SD转换从采样的模拟值产生数字输出值的MSB。 在SD相结束时，采样的模拟值减少到残留在SD ADC积分器的电容器中的“残留量化误差”。 在分辨率提升阶段，使用提供至少LSB的第二SD转换，从残余量化误差产生数字输出值的LSB。
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公开(公告)号：US08890577B1
公开(公告)日：2014-11-18
申请号：US14157316
申请日：2014-01-16
Applicant: Linear Technology Corporation
Inventor： Gerd Trampitsch
CPC classification number: G11C27/02 , G11C27/024 , G11C27/026 , H03K5/2481 , H03M1/1245
Abstract: A method and a circuit achieve fully isolated sampling of bipolar differential voltage signals. The isolated sampling network is suitable for applications in which sampling signals far outside of the supply voltages are desired. A sampling network of the present invention may sample a differential signal between voltages −VDSMAX and VDSMAX, even with common mode voltages that exceed the supply voltage (e.g., an input stage of an ADC). The bipolar isolated input sampling network may include a polarity comparator and sampling switches that operate as rectifiers. Rectification ensures that a unipolar sampling network needs only to sample signals of predetermined voltage levels.
Abstract translation: 一种方法和电路实现了双极差分电压信号的完全隔离采样。 隔离采样网络适用于远远超出供电电压范围的采样信号的应用。 本发明的采样网络即使在超过电源电压的共模电压（例如，ADC的输入级）上也可以对电压-VDSMAX和VDSMAX之间的差分信号进行采样。 双极隔离输入采样网络可以包括作为整流器工作的极性比较器和采样开关。 整流确保单极采样网络仅需要采样预定电压电平的信号。
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