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公开(公告)号：US20160285776A1
公开(公告)日：2016-09-29
申请号：US14664944
申请日：2015-03-23
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Chen Gaist , Ran Ravid , Liron Mulla , Avner Hadash
IPC: H04L12/801
CPC classification number: H04L47/35 , H04L1/00 , H04L1/0002 , H04L1/0034 , H04L1/18 , H04L47/28 , H04L47/34
Abstract: A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.
Abstract translation: 一种用于通信的方法包括：通过通信链路从网络节点向对等节点发送出站数据块序列，以及从所述对等节点接收传入数据块。 控制字段由网络节点添加到序列中的每个输出数据块中的预定位置。 在序列中的输出数据块的至少第一子集中，控制字段包含错误控制信息，该错误控制信息能够使对等节点向网络节点重传一个或多个输入数据块，同时至少 所述序列中的所述输出数据块的第二子集与所述第一子集不相交，所述控制字段包含流控制指令，被配置为使所述对等节点改变所述输入数据块在所述链路上的传输速率。
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公开(公告)号：US11934568B2
公开(公告)日：2024-03-19
申请号：US17115832
申请日：2020-12-09
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Zachy Haramaty , Zvika Eyal , Shachar Dor , Liron Mula , Barry Spinney
CPC classification number: G06F21/85 , G06F13/4068 , G06F21/73 , G06F21/86 , G06F2221/2103
Abstract: A device including a cable transceiver including cable electrical connections including data electrical connections and control electrical connections, and a hardware memory device, the hardware memory device storing a string identifying a cable and being electrically accessible from externally to the cable transceiver via the control electrical connections. The cable, in electrical connection with the cable electrical connections, may be included in the device. A device for verifying cable authenticity is also described, the device including interface hardware for interfacing a plurality of cables with the device, and verifier circuitry configured to verify that each of the plurality of cables is genuine based on a string stored in a hardware memory device included in each of the plurality of cables. Related apparatus and methods are also described.
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公开(公告)号：US11750699B2
公开(公告)日：2023-09-05
申请号：US17147487
申请日：2021-01-13
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Daniel Marcovitch , Larry R. Dennison , Aviad Levy , Noam Bloch , Gil Bloch
IPC: H04L67/1097 , H04L67/60
CPC classification number: H04L67/1097 , H04L67/60
Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.
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公开(公告)号：US11711294B2
公开(公告)日：2023-07-25
申请号：US17246736
申请日：2021-05-03
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Aviv Kfir , Barak Gafni , Ilya Vershkov
CPC classification number: H04L45/24 , H04L45/22 , H04L45/566
Abstract: A network device includes processing circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The processing circuitry is configured to select a first port among the multiple ports to serve as an egress port for a packet, and to forward the packet to the first port, irrespective of whether or not the first port is usable as the egress port. The processing circuitry is further configured to, when the first port is usable as the egress port, transmit the packet to the communication network via the first port, and when the first port is unusable as the egress port, forward the packet from the first port to a second port among the multiple ports and transmit the packet to the communication network via the second port.
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公开(公告)号：US11637739B2
公开(公告)日：2023-04-25
申请号：US17145341
申请日：2021-01-10
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Niv Aibester , Aviv Kfir , Gil Levy , Liron Mula
IPC: H04L41/06
Abstract: A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.
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Patent Agency Ranking
公开(公告)号：US11558316B2
公开(公告)日：2023-01-17
申请号：US17175716
申请日：2021-02-15
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Liron Mula , Idan Matari , Niv Aibester , George Elias , Lion Levi
IPC: H04L12/861 , H04L49/90 , H04L47/32 , H04L49/9047
Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.
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公开(公告)号：US11552882B2
公开(公告)日：2023-01-10
申请号：US17211904
申请日：2021-03-25
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Jose Yallouz , Lion Levi , Gil Mey-Tal , Daniel Klein
IPC: H04L12/703 , H04L12/721 , H04L12/707 , H04L12/717 , H04L45/28 , H04L45/42 , H04L45/00 , H04L45/12
Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.
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公开(公告)号：US11502912B2
公开(公告)日：2022-11-15
申请号：US17137729
申请日：2020-12-30
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Gil Levy , Pedro Reviriego , Salvatore Pontarelli
Abstract: A network device includes at least one communication ingress port, ingress packet processing circuitry and a packet-action cache memory (PACM). The at least one communication ingress port is configured to receive packets including packet headers from a network. The ingress packet processing circuitry is configured to receive the packets and to process the packets in accordance with respective packet actions specified for the packets. The PACM is configured to store one or more of the packet actions in association with one or more respective fingerprints which are calculated over the packet headers of the corresponding packets, for use by the ingress packet processing circuitry. The fingerprints are smaller than the corresponding packet headers.
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公开(公告)号：US20220311702A1
公开(公告)日：2022-09-29
申请号：US17211904
申请日：2021-03-25
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Jose Yallouz , Lion Levi , Gil Mey-Tal , Daniel Klein
IPC: H04L12/703 , H04L12/721 , H04L12/707 , H04L12/717
Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.
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公开(公告)号：US11425027B2
公开(公告)日：2022-08-23
申请号：US17086412
申请日：2020-11-01
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Michael Gandelman , Jose Yallouz , Lion Levi , Tamir Ronen , Aviad Levy , Vladimir Koushnir
IPC: H04L45/00 , H04L45/02 , H04L45/122 , H04L49/00
Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.
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