公开(公告)号：US20080049482A1

公开(公告)日：2008-02-28

申请号：US11925208

申请日：2007-10-26

申请人： Douglas PERRY ,  Peter GILLINGHAM

发明人： Douglas PERRY ,  Peter GILLINGHAM

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.

摘要翻译： 公开了三元内容可寻址存储器（CAM）单元，用于在不匹配的情况下提供缩减或最小化匹配线（ML）电容并用于增加匹配线和尾线之间的电流。 CAM单元的速度通常与其ML电容成反比，并且与电流成比例。 传统的三元CAM单元具有许多匹配线晶体管，每个有助于匹配线电容。 本发明的实施例在CAM单元的匹配线和接地线或尾线之间具有单个匹配线晶体管。 单个匹配线晶体管响应于来自比较电路的放电信号将匹配线耦合到尾线。 比较电路可以分为用于驱动栅极电压电平控制节点的上拉部分和用于放电栅极电压电平控制节点的放电部分，放电信号被提供在栅极电压电平控制节点处。

公开(公告)号：US20080005518A1

公开(公告)日：2008-01-03

申请号：US11477659

申请日：2006-06-30

申请人： Peter Gillingham ,  Robert McKenzie

发明人： Peter Gillingham ,  Robert McKenzie

IPC分类号： G06F13/00

CPC分类号： G06F13/4243 ,  G11C7/1066 ,  G11C29/50012 ,  G11C2207/2254

摘要： A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

摘要翻译： 提供了一种快照数据训练方法，用于在单次读取操作中确定DQS使能信号的最佳定时。 这是通过首先将格雷码计数序列写入存储器，然后在单个脉冲串中读回来完成的。 控制器从发出命令的时间开始以固定的时间间隔对读取脉冲串进行采样，以确定环路延迟。 简单的真值表查找确定正常读取的最佳DQS使能定时。 有利地，在正常读取操作期间，使能的DQS信号的第一上升沿用于对每次发出命令时启用的计数器进行采样。 如果计数器样本发生变化，则指示定时漂移已经发生，可以调整DQS使能信号以补偿漂移并保持以DQS前导码为中心的位置。 该技术也可以应用于使用迭代方法来确定上电时的DQS使能定时的系统。 本发明的另一个实施例是基于柜台的DQS锁存样本的简单的低延迟时钟域交叉电路。

公开(公告)号：US07304876B2

公开(公告)日：2007-12-04

申请号：US11534873

申请日：2006-09-25

申请人： Douglas Perry ,  Peter Gillingham

发明人： Douglas Perry ,  Peter Gillingham

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.

摘要翻译： 公开了三元内容可寻址存储器（CAM）单元，用于在不匹配的情况下提供缩减或最小化匹配线（ML）电容并用于增加匹配线和尾线之间的电流。 CAM单元的速度通常与其ML电容成反比，并且与电流成比例。 传统的三元CAM单元具有许多匹配线晶体管，每个有助于匹配线电容。 本发明的实施例在CAM单元的匹配线和接地线或尾线之间具有单个匹配线晶体管。 单个匹配线晶体管响应于来自比较电路的放电信号将匹配线耦合到尾线。 比较电路可以分为用于驱动栅极电压电平控制节点的上拉部分和用于放电栅极电压电平控制节点的放电部分，放电信号被提供在栅极电压电平控制节点处。

公开(公告)号：US07251148B2

公开(公告)日：2007-07-31

申请号：US11269659

申请日：2005-11-09

申请人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

发明人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C15/04 ,  G11C15/043

摘要： A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

摘要翻译： 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前，该电路首先将匹配线预先接地，并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后，匹配线上的感测数据将被锁存，并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD，所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位，匹配线感测操作速度增加。

公开(公告)号：US20050276086A1

公开(公告)日：2005-12-15

申请号：US10856783

申请日：2004-06-01

申请人： Douglas Perry ,  Peter Gillingham

发明人： Douglas Perry ,  Peter Gillingham

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04

摘要： A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.

摘要翻译： 公开了三元内容可寻址存储器（CAM）单元，用于在不匹配的情况下提供缩减或最小化匹配线（ML）电容并用于增加匹配线和尾线之间的电流。 CAM单元的速度通常与其ML电容成反比，并且与电流成比例。 传统的三元CAM单元具有许多匹配线晶体管，每个有助于匹配线电容。 本发明的实施例在CAM单元的匹配线和接地线或尾线之间具有单个匹配线晶体管。 单个匹配线晶体管响应于来自比较电路的放电信号将匹配线耦合到尾线。 比较电路可以分为用于驱动栅极电压电平控制节点的上拉部分和用于放电栅极电压电平控制节点的放电部分，放电信号被提供在栅极电压电平控制节点处。

公开(公告)号：US20050265506A1

公开(公告)日：2005-12-01

申请号：US11195257

申请日：2005-08-01

申请人： Richard Foss ,  Peter Gillingham ,  Graham Allan

发明人： Richard Foss ,  Peter Gillingham ,  Graham Allan

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03D3/24 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

摘要： A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.

摘要翻译： 包括用于同步存储器的时钟施加电路或用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置，以及用于接收时钟输入信号并用于传送时钟的抽头延迟线 驱动信号与时钟输入信号同步但延迟到同步存储器，延迟是时钟周期或时钟输入信号的一小部分。

公开(公告)号：US06510503B2

公开(公告)日：2003-01-21

申请号：US09182494

申请日：1998-10-30

申请人： Peter Gillingham ,  Bruce Millar

发明人： Peter Gillingham ,  Bruce Millar

IPC分类号： G06F1300

CPC分类号： G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

摘要： This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

公开(公告)号：US5694143A

公开(公告)日：1997-12-02

申请号：US253271

申请日：1994-06-02

申请人： Dennis Fielder ,  James Derbyshire ,  Peter Gillingham ,  Randy Torrance ,  Cormac O'Connell

发明人： Dennis Fielder ,  James Derbyshire ,  Peter Gillingham ,  Randy Torrance ,  Cormac O'Connell

IPC分类号： G06T1/20 ,  G06F3/153 ,  G06F12/00 ,  G06F13/16 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4093 ,  G11C11/4096 ,  H01L27/10

CPC分类号： G09G5/363 ,  G09G5/39 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/1048 ,  G11C2207/104

摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

摘要翻译： 一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中 作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。

公开(公告)号：US4653017A

公开(公告)日：1987-03-24

申请号：US783554

申请日：1985-10-03

申请人： Roger Colbeck ,  Peter Gillingham

发明人： Roger Colbeck ,  Peter Gillingham

IPC分类号： H03H19/00 ,  G06G7/00

CPC分类号： H03H19/004

摘要： A decimating filter utilizing first and second switched input capacitors for sampling an input signal on opposite phases of a first sampling clock signal. The switched input capacitors are connected to an integrating circuit for filtering the sampling signal. An output of the integrating circuit is sampled according to a second sampling clock signal having a frequency equal to a submultiple of the first sampling clock signal frequency. By sampling the input signal on opposite phases, the input signal is effectively sampled at twice the first sampling clock signal frequency. Accordingly, in applications involving high sampling frequencies, such as digital signal transmission, the input signal can be sampled at a sufficiently high frequency without requiring a prohibitively high input sampling clock frequency. The decimating filter is of simple design and can be inexpensively implemented on an integrated circuit chip requiring small area.

摘要翻译： 抽取滤波器利用第一和第二开关输入电容器对第一采样时钟信号的相反相位上的输入信号进行采样。 开关输入电容器连接到用于滤波采样信号的积分电路。 积分电路的输出根据具有等于第一采样时钟信号频率的倍数的频率的第二采样时钟信号进行采样。 通过对相位相位的输入信号采样，输入信号以两倍于第一采样时钟信号频率进行有效采样。 因此，在涉及高采样频率（例如数字信号传输）的应用中，可以以足够高的频率对输入信号进行采样，而不需要非常高的输入采样时钟频率。 抽取滤波器设计简单，可以在需要小面积的集成电路芯片上廉价实施。

公开(公告)号：US20120126849A1

公开(公告)日：2012-05-24

申请号：US13284338

申请日：2011-10-28

申请人： Peter Gillingham

发明人： Peter Gillingham

IPC分类号： H03K19/003

CPC分类号： H03K3/012 ,  H01L2924/0002 ,  H03K19/0005 ,  H03K19/00361 ,  H04L25/0278 ,  H01L2924/00

摘要： In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

摘要翻译： 在具有连接到内部部分的端子的半导体器件中，用于为器件的端子提供管芯端接的终端电路。 终端电路包括多个晶体管，其包括连接在端子和电源之间的至少一个NMOS晶体管和至少一个PMOS晶体管; 以及控制电路，用于以相应的NMOS栅极电压驱动每个NMOS晶体管的栅极并且用相应的PMOS栅极电压驱动每个PMOS晶体管的栅极，所述控制电路被配置为控制NMOS和PMOS栅极电压，以便 当使能片上端接时，将晶体管置于欧姆区域。 电源提供小于每个所述NMOS栅极电压并大于每个所述PMOS栅极电压的电压。