公开(公告)号：US6040995A

公开(公告)日：2000-03-21

申请号：US230614

申请日：1999-01-28

Applicant: Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

Inventor： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

IPC: H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

CPC classification number: H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

Abstract translation: PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

公开(公告)号：US6022786A

公开(公告)日：2000-02-08

申请号：US32484

申请日：1998-02-27

Applicant: Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

Inventor： Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10861

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Abstract translation: 为了制造电容器，特别是用于动态存储单元布置，在衬底中蚀刻沟槽。 在沟槽中，产生层序列，其交替地包含掺杂的硅和含锗层的层。 通过各向异性蚀刻，半导体衬底（12）的表面暴露在沟槽底板的区域中。 沟槽填充有导电支撑结构（20）。 含锗层被选择性地去除掺杂硅层。 掺杂硅（17）和支撑结构（20）的层的暴露表面设置有电容器电介质（22），其上施加有对电极（23）。

公开(公告)号：US5643836A

公开(公告)日：1997-07-01

申请号：US279106

申请日：1994-07-22

Applicant: Thomas Meister ,  Reinhard Stengl

Inventor： Thomas Meister ,  Reinhard Stengl

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/469 ,  H01L21/768 ,  H01L21/465

CPC classification number: H01L21/76819 ,  H01L21/31055

Abstract: An insulating layer is applied onto the surface of a semiconductor layer structure having elevations up to a maximum step height. The thickness of the insulating layer is greater than the maximum step height. The insulating layer is structured to have irregularities with an essentially identical lateral expanse in the region of the edges of the elevations. The irregularities are planarized by chemical mechanical polishing and/or by deposition, flowing and etch-back of a planarization layer.

Abstract translation: 将绝缘层施加到具有高达最大台阶高度的高度的半导体层结构的表面上。 绝缘层的厚度大于最大台阶高度。 绝缘层被构造成具有在高度边缘的区域中具有基本相同的横向宽度的凹凸。 通过化学机械抛光和/或通过平坦化层的沉积，流动和蚀刻来使不规则性平坦化。

公开(公告)号：US5498567A

公开(公告)日：1996-03-12

申请号：US379861

申请日：1995-04-03

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) selectively etching the first layer with respect to the substrate and the second layer so as to provide an undercut between the second layer and the surface of the substrate; f) forming a single crystal region on the exposed surface of the substrate by selective epitaxy: g) doping the second layer such that parts of the second layer adjoining the single-crystal region acting as a channel region form a source region and a drain region; h) producing a gate dielectric at a surface of the single-crystal region; and i) forming a gate electrode that is insulated from the source and drain regions on the gate dielectric.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）相对于所述基底和所述第二层选择性地蚀刻所述第一层，以便在所述第二层和所述基底的表面之间提供底切; f）通过选择性外延在衬底的暴露表面上形成单晶区域：g）掺杂第二层，使得与用作沟道区的单晶区相邻的第二层的部分形成源区和漏区 ; h）在单晶区域的表面产生栅电介质; 以及i）形成与栅极电介质上的源极和漏极区域绝缘的栅电极。

公开(公告)号：US5422303A

公开(公告)日：1995-06-06

申请号：US185514

申请日：1994-01-24

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) covering surfaces and sidewalls of the second layer with a third layer f) selectively etching the first layer with respect to the substrate and the second layer and the third layer so as to provide an undercut between the second layer and the surface of the substrate; g) forming a single crystal region on the exposed surface of the substrate by selective epitaxy without nucleation occurring at the surface of the third layer; h) forming a collector in the substrate under the single-crystal region; i) forming a base in the single-crystal region; j) doping and configuring the second layer such that it forms a base terminal; and k) forming an emitter above the base.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）用第三层覆盖第二层的表面和侧壁f）相对于衬底和第二层和第三层选择性地蚀刻第一层，以便在第二层和衬底的表面之间提供底切 ; g）通过选择性外延在第三层的表面上没有成核而在衬底的暴露表面上形成单晶区; h）在单晶区域下在衬底中形成集电体; i）在单晶区域形成碱; j）掺杂和配置第二层，使得它形成基极; 和k）在基底上形成发射体。

公开(公告)号：US5306647A

公开(公告)日：1994-04-26

申请号：US998611

申请日：1992-12-30

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Wolfgang Hoenlein ,  Josef Willer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Wolfgang Hoenlein ,  Josef Willer

IPC: C25F3/12 ,  H01L21/3063 ,  H01L31/0352 ,  H01L31/047 ,  H01L31/18

CPC classification number: H01L31/1804 ,  H01L21/3063 ,  H01L31/03529 ,  H01L31/047 ,  Y02E10/547 ,  Y02P70/521

Abstract: A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.

Abstract translation: 通过用于制造太阳能电池的电化学蚀刻，从n掺杂的单晶硅的衬底晶片剥离n掺杂单晶硅的自支撑层。 通过电化学蚀刻，特别是在其中衬底晶片作为阳极连接的含氟化物的酸性电解质中，在衬底晶片中形成孔。 当达到基本上对应于自支撑层的厚度的孔的深度时，蚀刻的工艺参数被修改，使得自支撑层由于孔一起生长而被剥离。 该太阳能电池由自支撑层制造，并且可以在相同的基板晶片上重复地施加该方法以剥离多个自支撑层。

公开(公告)号：US5113237A

公开(公告)日：1992-05-12

申请号：US698332

申请日：1991-05-06

Applicant: Reinhard Stengl

Inventor： Reinhard Stengl

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/732 ,  H01L29/74 ,  H01L29/861

CPC classification number: H01L29/404 ,  H01L29/0615

Abstract: A planar pn-junction with high electric strength, which separates a semiconductor region inserted in a semiconductor body from the rest of the semiconductor body, has, in its border region, a plurality of field plates which are separated from a semiconductor zone residing below and extending the semiconductor region by an electrically insulating layer. The field plates contact the semiconductor zone in the area of contact holes. The contact holes respectively have set distances between them and the inner and outer field plate edges, whereby below those field plate parts residing between the contact holes and the inner field plates borders, local doping maxima of the semiconductor zone are provided.

Abstract translation: 将半导体本体中插入的半导体区域与半导体本体的其余部分分离的具有高电强度的平面pn结在其边界区域中具有多个场板，该场板与位于半导体主体的下方的半导体区域分离， 通过电绝缘层延伸半导体区域。 场板接触接触孔区域的半导体区。 接触孔分别具有它们与内外板边缘之间的设定距离，由此在位于接触孔和内场板边界之间的场板部分的下方，提供半导体区域的局部掺杂最大值。

公开(公告)号：US4907056A

公开(公告)日：1990-03-06

申请号：US248150

申请日：1988-09-23

Applicant: Ulrich Goesele ,  Reinhard Stengl

Inventor： Ulrich Goesele ,  Reinhard Stengl

IPC: H01L29/06 ,  H01L29/74 ,  H01L29/861

CPC classification number: H01L29/0615 ,  H01L29/7424

Abstract: A semiconductor region that is inserted into a semiconductor member is provided, the latter being separated from the former by a planar pn junction including a first, more highly doped sub-region and a second, more lightly doped sub-region that is limited by a part of the pn junction that gradually approaches a boundary surface of the semiconductor member. An electrode contacts the semiconductor region and covers a part of the second sub-region and extends toward the lateral limitation of the semiconductor region to such an extent that, given the application of a voltage inhibiting the pn junction the space charge zone forming thereat has its edge lying in the boundary surface just reaching the electrode edge given a reduced breakdown voltage.

Abstract translation: 设置插入到半导体部件中的半导体区域，后者通过平面pn结与前者分离，该平面pn结包括第一，更高掺杂的子区和第二，更轻掺杂的子区，该子区被 pn结的部分逐渐接近半导体部件的边界面。 电极接触半导体区域并且覆盖第二子区域的一部分并且朝向半导体区域的横向限制延伸到这样的程度，即，在施加抑制pn结的电压的情况下，在其上形成的空间电荷区域具有其 边缘位于刚刚到达电极边缘的边界表面，给出了降低的击穿电压。

公开(公告)号：US08178966B2

公开(公告)日：2012-05-15

申请号：US12940713

申请日：2010-11-05

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L21/36

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。

公开(公告)号：US07872349B2

公开(公告)日：2011-01-18

申请号：US11324789

申请日：2006-01-03

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schaefer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schaefer

IPC: H01L23/473

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。