公开(公告)号：US07704840B2

公开(公告)日：2010-04-27

申请号：US11611784

申请日：2006-12-15

Applicant: Igor Peidous ,  Rohit Pal

Inventor： Igor Peidous ,  Rohit Pal

IPC: H01L21/336

CPC classification number: H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。 应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。

公开(公告)号：US20100090289A1

公开(公告)日：2010-04-15

申请号：US12249570

申请日：2008-10-10

Applicant: Frank Bin YANG ,  Rohit PAL ,  Michael J. HARGROVE

Inventor： Frank Bin YANG ,  Rohit PAL ,  Michael J. HARGROVE

IPC: H01L47/00 ,  H01L21/3205

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

Abstract translation: 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源极和漏极区域，其中沟道区域位于源极和漏极区域之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US20100081245A1

公开(公告)日：2010-04-01

申请号：US12240682

申请日：2008-09-29

Applicant: Frank Bin YANG ,  Rohit PAL ,  Michael J. HARGROVE

Inventor： Frank Bin YANG ,  Rohit PAL ,  Michael J. HARGROVE

IPC: H01L21/336

CPC classification number: H01L29/7847 ,  H01L29/66636

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract translation: 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，沉积覆盖栅电极的应力诱导层，退火含硅衬底以重结晶 栅电极，去除应力诱导层，使用栅电极作为蚀刻掩模蚀刻到衬底中的凹槽，以及在凹槽中外延生长杂质掺杂的含硅区域。

公开(公告)号：US20100059852A1

公开(公告)日：2010-03-11

申请号：US12209056

申请日：2008-09-11

Applicant: Rohit PAL ,  David BROWN ,  Scott LUNING

Inventor： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device structure is provided. The method begins by providing a substrate having a layer of semiconductor material, a pad oxide layer overlying the layer of semiconductor material, and a pad nitride layer overlying the pad oxide layer. The method proceeds by selectively removing a portion of the pad nitride layer, a portion of the pad oxide layer, and a portion of the layer of semiconductor material to form an isolation trench. Then, the isolation trench is filled with a lower layer of isolation material, a layer of etch stop material, and an upper layer of isolation material, such that the layer of etch stop material is located between the lower layer of isolation material and the upper layer of isolation material. The layer of etch stop material protects the underlying isolation material during subsequent fabrication steps.

Abstract translation: 提供一种制造半导体器件结构的方法。 该方法开始于提供具有半导体材料层的衬底，覆盖在半导体材料层上的衬垫氧化物层和覆盖衬垫氧化物层的衬垫氮化物层。 该方法通过选择性地去除衬垫氮化物层的一部分，衬垫氧化物层的一部分和半导体材料层的一部分来形成隔离沟槽。 然后，隔离沟槽填充有较低层的隔离材料，一层蚀刻停止材料和上层隔离材料，使得该蚀刻停止材料层位于隔离材料的下层和上部隔离层之间 隔离材料层。 蚀刻停止材料层在随后的制造步骤期间保护下面的隔离材料。

公开(公告)号：US07632727B2

公开(公告)日：2009-12-15

申请号：US12119384

申请日：2008-05-12

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

IPC: H01L29/772

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract translation: 提供一种制造半导体晶体管器件的方法。 制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。 然后，围绕栅极结构的侧壁形成间隔物。 接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。 在该步骤中，栅极结构和间隔物用作离子注入掩模。 离子在半导体材料中形成非晶化区域。 此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。 此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

公开(公告)号：US20090256201A1

公开(公告)日：2009-10-15

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

Inventor： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US20080248598A1

公开(公告)日：2008-10-09

申请号：US11697955

申请日：2007-04-09

Applicant: Rohit Pal ,  Alok Vaid

Inventor： Rohit Pal ,  Alok Vaid

IPC: H01L21/66 ,  H01L21/306 ,  H01L23/58

CPC classification number: H01L22/12

Abstract: A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.

Abstract translation: 一种方法包括照亮包括至少部分地形成在半导体材料中的第一多个应力材料区域的第一栅格的至少一部分。 测量从第一格栅的照明部分反射的光以产生第一反射曲线。 基于第一反射曲线确定第一多个应力材料区域的特性。 测试结构包括相对于半导体层的表面凹陷并限定第一格栅的第一多个应力材料区域。 半导体层的第一多个暴露部分设置在第一多个应力材料区域中的每一个之间。

公开(公告)号：US08664066B2

公开(公告)日：2014-03-04

申请号：US13552722

申请日：2012-07-19

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract translation: 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

公开(公告)号：US08390042B2

公开(公告)日：2013-03-05

申请号：US13353013

申请日：2012-01-18

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L29/43 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 包括金属栅电极的改进的半导体器件通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度而形成，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US20120208337A1

公开(公告)日：2012-08-16

申请号：US13456633

申请日：2012-04-26

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。