公开(公告)号：US10359800B2

公开(公告)日：2019-07-23

申请号：US15693214

申请日：2017-08-31

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Serge Ramet ,  Sandrine Nicolas ,  Danika Perrin ,  Cedric Rechatin

IPC: G05F1/10 ,  G05F3/02 ,  G05F3/26 ,  H03F3/195 ,  G05F1/46 ,  H03F3/16

Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.

公开(公告)号：US10303192B2

公开(公告)日：2019-05-28

申请号：US15364392

申请日：2016-11-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Alexandre Pons

IPC: H02J7/00 ,  G05F1/59 ,  G05F1/56 ,  G05F1/569 ,  H01R24/60 ,  H02J7/02 ,  H02J7/06 ,  H03F3/45 ,  H01R107/00 ,  H02J7/10

Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.

公开(公告)号：US10254781B2

公开(公告)日：2019-04-09

申请号：US15722404

申请日：2017-10-02

Applicant: STMicroelectronics (Alps) SAS

Inventor： Kuno Lenz

IPC: G05F3/26 ,  G05F1/46 ,  H02J7/34

Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.

公开(公告)号：US20190094895A1

公开(公告)日：2019-03-28

申请号：US16130706

申请日：2018-09-13

Applicant: STMicroelectronics (Alps) SAS

Inventor： Kuno Lenz

IPC: G05F1/575 ,  H02M3/158

Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.

公开(公告)号：US20190074763A1

公开(公告)日：2019-03-07

申请号：US16103582

申请日：2018-08-14

Applicant: STMicroelectronics (Alps) SAS

Inventor： Alexandre Pons

IPC: H02M3/156 ,  G05F5/00

Abstract: A method can be used for compensating a voltage drop on a cable connected between a source device and a receiver device. The source device delivers an offset current on a channel configuration pin of the source device, the offset current causing an increase in a voltage on the channel configuration pin of the source device to a chosen reference voltage. The offset current is stored in the source device. The source device absorbs an absorption current originating from the channel configuration pin of the source device, the absorption current depending on the stored offset current and on the voltage drop. The source device generates a compensated supply voltage on a power supply pin of the source device, the compensated supply voltage equal to a reference supply voltage increased by the voltage drop to within a tolerance.

公开(公告)号：US20190067180A1

公开(公告)日：2019-02-28

申请号：US16110121

申请日：2018-08-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David AUCHERE ,  Laurent SCHWARZ ,  Deborah COGONI ,  Eric SAUGIER

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16235 ,  H05K1/185 ,  H05K2201/10621 ,  H05K2201/10636

Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.

公开(公告)号：US20190027925A1

公开(公告)日：2019-01-24

申请号：US16026503

申请日：2018-07-03

Applicant: STMicroelectronics(Alps) SAS

Inventor： Frederic Lebon ,  Laurent Chevalier

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  G06F1/26

Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

公开(公告)号：US10073474B2

公开(公告)日：2018-09-11

申请号：US15251289

申请日：2016-08-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Patrik Arno ,  Alexandre Balmefrezol

IPC: G06F1/20 ,  G05F1/46

CPC classification number: G05F1/46

Abstract: A method of controlling a current flowing through a load including the steps of: applying a first transfer function representative of the load to a first voltage to obtain a second voltage; applying the second voltage to a first terminal of a circuit for generating the current; sampling a third voltage between first and second terminals of the load; comparing the third voltage with the second voltage; and determining the current to be supplied to the load according to the result of the comparison.

公开(公告)号：US10067550B2

公开(公告)日：2018-09-04

申请号：US15253012

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Fabien Journet

IPC: G06F1/32 ,  G06F9/38 ,  H04B5/00 ,  G06F1/06

Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

公开(公告)号：US20180130492A1

公开(公告)日：2018-05-10

申请号：US15867223

申请日：2018-01-10

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jonathan Cottinet ,  Jean Claude Bini

IPC: G11B20/10 ,  H04B15/04 ,  G06F3/16 ,  H04L7/04

CPC classification number: G11B20/10222 ,  G06F3/165 ,  H04B15/04 ,  H04B2215/065 ,  H04L7/04

Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.